Virtual Design Chains At The EDA Forum

The German edacentrum’s EDA Forum was held in Berlin, Germany, in early November. It was very interesting to see the design chain effects in the automotive domain, very visible in a panel yours truly was part of, together with Audi, Bosch, Infineon, MicroChip, Synopsys, Mentor, and the BMBF. Driven from the top of the design chain, the direction is clearly to go more virtual to optimize the communication and to have the ability to interact between suppliers and users.

Being a “Berliner” myself, it did not take me long to accept the invitation to be on a panel discussion in my hometown. Moderated by Professor Nebel, the founder of one of the startups I worked for in my past, the panel assembly was quite fascinating as it represented a fairly complete design chain.

Picture Credit: edacentum
From Left to Right – Berthold Hellenthal (AUDI), Erich Biermann (Bosch), Matthias Knoppik (Mentor, a Siemens Business), Stefan Mengel (BMBF), Wolfgang Nebel (OFFIS), Frank Schirrmeister (Cadence), Andreas Hoffmann (Synopsys), Matthias Kästner (Microchip), Hartmut Hiller (Infineon)

At the top of the design chain, Berthold Hellenthal was representing the car maker Audi, the OEM that interacts with the end customer. For quite some time, Audi has been at the forefront of enhancing the development process to add in more virtualization, so the topic of virtual platforms was a topic of discussion. While there is a clear need for real hardware during verification and testing, Hellenthal reconfirmed the message he had clearly given last year at DVCON Europe: virtual platforms are key to help optimize and parallelize the development process, from semiconductors to systems. His DVCON slide set is here.

Next in the design chain was Erich Biermann representing Bosch. As a direct tier 1 supplier to the OEMs, Bosch is directly selling to the car manufacturers, and, as such, an intermediary between the tier 2 semiconductor vendors and the OEMs. They supply the ECUs. Virtualization with virtual platforms is a tremendous help here as they can take models coming from the semiconductor vendor and integrate them into virtual ECUs. Slide 25 in Berthold Hellenthal’s DVCON Keynote nicely shows how this allows the interaction and integration across several vendors, and Eric Biermann confirmed how Bosch is working on virtualization techniques accordingly.

Both present semiconductor vendors on the panel, Hartmut Hiller from Infineon and Matthias Kästner from Microchip were put into the spotlight when some challenges were discussed. Even within one company, the interfaces for models used in virtual platforms may not always be as interoperable as consumers wish. We EDA vendors on the panel pointed to the standardization efforts in that domain, but it was very clear from the discussion that we have some way to go here, despite the industry’s efforts to align with SystemC TLM 2.0 back in 2008 on an infrastructure for integration of transaction-level models. There is clearly more work to be done here, and it is underway in the appropriate industry working groups like Accellera and IEEE.

Some other interesting discussion points were debated during the evening. With virtual platforms basically being invented in the late 90s by the “Three Vs” (Virtio, Virtutech, and VaST), what innovations should we focus on from here, as we are now 20 years on? Where has the innovation been at all? That brought up some business aspects. For instance, SystemC AMS for mixed signal is out there, but the commercial viability is not 100% clear yet. In addition, when talking design chains, the effort to enable virtualization must be commercially viable for every part of the design chain. Starting from processor models through the effort to build a virtual SoC and then integrate it into Virtual ECUs, which are then integrated into virtual models representing car electronics and to develop software on it, the efforts at every step are not insignificant. “Feeding” the design chain may turn out to be nontrivial.

One question on the panel that was directly addressed to me was around EDA’s activities in machine learning (ML) and artificial intelligence (AI). Our position at Cadence—and in my domain of verification—centers around both optimizing our tools using ML inside and ML outside, as well as enablement of silicon and systems in the AI/ML domain. Cadence President Anirudh Devgan has outlined the vision in his discussion with Ed Sperling in a write-up called “Where ML Works Best.” And with the research funding division BMBF on the panel, there was some discussion here about how to further strengthen Germany and Europe in that area.

Overall, there is lots of interesting and fun work ahead to enable virtualization, in Europe and worldwide, so the future is bright. As some observed, the audience in the room did know each other quite well and there was also lots of grey hair visible—some fresh blood is definitely desirable!