Week 19: Ready. Steady. Go!

The window for submitting to the IP and designer tracks opens on Oct. 23. It’s time to get ready and check with your management if you can present your work at DAC. You can find the submission details and a link to last year’s content here. You can even browse presentation examples from past designer tracks.

If you are an EDA vendor, the designer track is a good opportunity for your users to submit content to DAC. The submissions will go through peer review, as we want to exclude overtly promotional presentations. This truly is a designer-to-designer forum. And because it’s vendor-independent, it is very different from the user group meetings common in our industry. Attendees get untarnished marketing-free content. (Which is not to imply that everything that marketing touches is suspect. I do run a corporate marketing department after all!)

The designer track has three submission categories: front-end silicon design, back-end silicon design, and embedded systems and software (ESS). If you follow my blog regularly you already know that ESS is a substantial part of DAC. We know that practitioners – EDA tool users, hardware designers, software engineers, application engineers or consultants – don’t necessarily write academic papers. So to be considered, all you have to do is submit a title, short abstract and six slides. DAC continues to foster this important community and next year we will have a dedicated designer track reception on the exhibit floor. I hope to see you there!

Now let me introduce you in more detail to our IP track chair, Adapt IP’s Mike McNamara, and one of our designer track co-chairs, Cadence’s Daniel Bourke. (Qualcomm’s Karam Chatha, the other designer track co-chair, will be introduced in a future blog.) With the window for submissions fast approaching, now is the time for you to get better acquainted.

Designer track co-chair Daniel Bourke currently works as director of North America field application engineering in Cadence’s Design IP group. He is responsible for developing AE team capabilities and operational processes to service Cadence’s fast growing IP product group’s customers. Dan has held other management roles in Cadence’s field applications organization focused mainly on simulation, formal and advanced verification technologies. Prior to Cadence Dan was a senior design engineer at Agilent and Redswitch Inc. working on storage, networking and backplane technologies. Dan started his career as a design engineer in Dublin, Ireland working for Silicon & Software Systems focused on the U.S. market. Dan graduated from Trinity College, Dublin, Ireland, with a B.Sc. in electrical/electronic engineering. Outside of work Dan loves spending time on sporting activities, from swimming to hiking, and can be seen on his road bike riding up Mt Tamalpais north of San Francisco most weekends.

IP track chair Mike McNamara’s early experience as a computer architect and chip designer (ESL/TRW, Cydrome, Ardent, Stardent) in the 1980s prepared and motivated him to be an EDA tool developer for more than two decades, starting in the 1990s. He developed VCS at Chronologic, SureCov at Surefire, and C-to-Silicon at Cadence). Mac left Cadence in 2012 to start Adapt IP, where he is leading the team that is building integrated circuits in an adaptable manner. More on Mac, from his grad school days at Cornell to his current gentleman farmer exploits (he owns the same farm in the Santa Cruz Mountains that the writer John Steinbeck did in 1930s), can be found in this EEWeb interview.

Mac told EEWeb that Steinbeck owned the farm in 1930s but never gave up writing, presumably in part because of the challenge of making a living as a farmer. I know that many of you find the prospect of writing a conference paper to be a challenge given the demands of your jobs. I would! Though for inspiration, check out Steinbeck’s Wikipedia entry. It lists 31 books to his credit, a few of which were published posthumously. Still, that’s nearly a book a year for his adult life, an impressive output, and one that perhaps makes the DAC requirements — remember, just a title, short abstract and six slides for the designer track! — seem a bit more manageable. Until next week.