Week In Review: Design, Low Power

Cadence added new machine learning functionality to its Xcelium Logic Simulator to speed verification closure on randomized regressions. Xcelium ML directly interfaces to the simulation kernel and learns iteratively over an entire simulation regression, guiding the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Kioxia adopted the updated tool and noted a 4X shorter turnaround time in our fully random regression runs to reach 99% function coverage of original.

Synopsys unveiled a virtual prototyping solution for the development of electric vehicle (EV) electronics hardware and software. It integrates versions of SaberRD, Virtualizer, Silver, and TestWeaver optimized for the needs of EV design, including EV model libraries for power electronic, microcontrollers and AUTOSAR components; functionality to support functional safety, HW/SW debug, variation analysis, coverage analysis and calibration design tasks; and APIs for integration into additional automotive flows and tools.

Spin Memory proposed a new design for memory, including DRAM, MRAM, and ReRAM, which it says allows for smaller cell footprints, improved densities, and row hammer protection. The company’s Universal Selector is a selective, vertical epitaxial cell transistor whose channel has a low enough doping concentration that it operates in full depletion. The channel is completely electrically isolated from the silicon substrate.

Truechip uncorked verification IP for USB4 and eUSB. The USB4 VIP supports Gen2 and Gen3, Thunderbolt, Power Delivery v3.0, and USB3.2, PCIe, and DisplayPort native tunneling over USB4 fabric. It also supports Reed Solomon-Forward Error Correction encoding/decoding and bandwidth arbitration and prioritization. The eUSB VIP supports eUSB2 PHY and eUSB2 fully compliant to the USB2.0 Revision 2.0 that supports high-speed, full-speed, and low-speed operation, eUSB device in native mode and USB2.0 operation based on repeater architecture, and register access protocol.

Mentor’s Calibre nmPlatform and Analog FastSPICE (AFS) custom and analog/mixed-signal circuit verification platform were qualified for Samsung Foundry’s 5/4nm finFET processes. Samsung worked with Mentor to customize automated PowerVia flow in Calibre YieldEnhancer for the maximum insertion of vias, and Calibre PERC Design Kit provides additional verification checks for electrostatic discharge and latch-up reliability.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

Hot Chips will be held as an online event Aug. 16-18. Tutorials on machine learning scale out and quantum computing will be held the 16^th with keynotes and architecture-focused sessions on the 17^th & 18^th. Live Q&A and discussion chat will accompany the broadcasts with recorded video available later for registered attendees.