Week In Review: Design, Low Power

IC/package co-design; exploring open RISC-V cores; TSMC certifications.


Tools & IP
Monozukuri unveiled its IC/Package co-design tool, GENIO. GENIO integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs.  It works seamlessly across all existing EDA flows and comprises floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization. Founded in 2014, Rome-based Monozukuri got its start with the HIPER project under the Europe’s Horizon 2020 funding.

BlueSpec debuted RISC-V Explorer, a free set of tools to evaluate and compare pre-tested, pre-built cores from RISC-V open source products. The first in a series of planned releases covers RV32IMAC cores from the CHIPS Alliance Rocket and Bluespec’s own Flute and Piccolo cores. Future releases will add cores from the OpenHW Group CV32, CHIPS Alliance SweRV, Incore Chromite, and Bluespec Magritte. An upcoming release will add support for connecting to the low cost Arty A7-100T FPGA board for high-speed execution and debugging.

Cadence launched its UltraLink D2D PHY IP on the TSMC N7 and N6 processes. Test silicon on the TSMC N7 process with full silicon characterization data is now available. The IP has been taped out on the TSMC N5 with test silicon availability anticipated later this year.

Sofics’ TakeCharge Electrostatic Discharge (ESD) portfolio and analog I/O are now available on TSMC’s 5nm process technology. The company says its ESD protection has been silicon proven by a customer on the node.

SimpleMachines developed its first-generation AI processor using Mentor’s Enterprise Verification Platform including the Questa simulation platform, verification IP for PCIe and HBM2, and Veloce Strato emulation hardware, as well as Mentor Consulting’s cloud-based Emulation-as-a-Service (EaaS) offering. SimpleMachines cited the ability to rapidly develop and differentiate AI system software a year before silicon.

Chelsio adopted Synopsys’ DesignWare 56G Ethernet PHY IP for the development of its SoC design targeting high-performance smart network interface card (NIC) and server applications. Chelsio cited support for a wide range of data rates from 1.25 Gbps to 56 Gbps across standards such as Ethernet, PCI Express, OIF, and JESD.

TSMC Certifications
Ansys’ multiphysics signoff solution was certified for TSMC’s 3nm (N3) process technology. RedHawk-SC for encompasses power network extraction, power integrity and reliability, signal EM, thermal reliability analysis for self-heat, thermal-aware EM and statistical EM budgeting, while Totem is similarly certified for transistor-level custom designs. TSMC also certified Ansys’ RedHawk and RaptorH families for its CoWoS with silicon interposer (CoWoS-S) and InFO with RDL interconnect (InFO-R) advanced packaging technologies.

Cadence’s digital full flow and custom tool suite achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s 3nm process technology. The digital flow includes improved extraction accuracy, updated routing rules, accurate LVF-generation during characterization and robust support of advanced coloring. The custom tool suite includes expanded 3nm design rule support, custom digital color remastering, enhanced analog cell support, additional productivity improvements with an enhanced device-level P&R flow and a front-to-back legacy-node design migration flow. TSMC also certified Cadence’s packaging reference flows for InFO-R and CoWoS-S. The latest reference flows offer a more efficient DRC signoff/tapeout methodology.

Synopsys’ digital and custom design platforms were certified for TSMC’s 3nm process technology. Tools produced by Synopsys have been optimized for the process. The digital flow added support for pin density aware placement and global route modeling for better routing convergence on standard cell pins, concurrent legalization and optimization for faster timing convergence, a new cell map infrastructure to maximize available white space to improve PPA, interconnect optimization by auto generating via pillar structures and partial parallel routing for HPC design, and power-aware mixed driving strength multi-bit flip flop optimization for low-power designs. TSMC also certified Synopsys’ CoWoS-S and InFO-R design flows based on the 3DIC Compiler unified platform, which is integrated with Ansys’ chip-package co-analysis solutions.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

Coming up soon is the 2nd IEEE International Conference on AI Circuits and Systems. AICAS2020 will be held as a virtual event on Aug. 31—Sept. 4 and feature presentations on neuromorphic systems, accelerators, designing for edge applications, algorithms, and HW/SW co-design for AI.

On Sept. 3rd, check out the RISC-V Global Forum (12am-6pm PT) to find out all the latest details about how the RISC-V ISA is being incorporated into diverse designs.

The ARC Virtual Processor Summit will take place Sept. 9-10 with a focus on automotive, edge AI, and high-performance embedded solutions.

Meanwhile, the Arm Research Summit will take place Sept. 9-11 with focuses on sustainability, data science, and security.

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