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Week In Review: Design, Low Power

Arm’s roadmap; 22nm analog IP; IP and tools for GF’s 12LP, 12LP+, 22FDX; MIPI A-PHY VIP.

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Tools & IP
Arm added two new platforms to its product roadmap: the Neoverse V1, and the Neoverse N2, the second-generation N-series platform. The V1 platform supports Scalable Vector Extensions (SVE), provides 50% better single-threaded performance over N1, and targets high-performance cloud, HPC, and machine learning applications. The N2 provides 40% higher single-threaded performance compared to N1 with the same power and area efficiency  and targets use cases such as cloud, SmartNICs and enterprise networking, and power-constrained edge devices.

Vidatronic unveiled a series of new 22nm analog IP: Low Dropout (LDO) Voltage Regulator IP for low-power applications, Bandgap Voltage Reference IP that includes an analog temperature sensor for voltage and temperature supervision, Oscillator IP with two very accurate clock outputs for system clock monitoring, Comparator IP with 4 programmable input threshold settings for voltage supervision, and 10-Bit SAR ADC/DAC IP which supports both ADC and DAC operating modes as well as fast and slow sampling modes for system testing.

SmartDV debuted verification IP to support the new MIPI A-PHY v1.0, a long-reach SerDes physical layer interface targeted at automotive applications such as ADAS and infotainment. The VIP can be used throughout a coverage-driven chip design verification flow in simulation, emulation, and FPGA prototyping. It includes SimXL Synthesizable Transactors for early software development on an FPGA platform.

GOWIN Semiconductor launched GoAI 2.0, a platform with an SDK and accelerator to perform machine learning for edge inference using convolutional neural networks on GOWIN FPGAs. It provides direct integration into TensorFlow and TensorFlow Lite ML platforms.

Allegro DVT released  its AL-D300 family of multi-format 8K60 video decoder IPs that support video decoding at rates of up to 8K60.

Rianta Solutions uncorked new 400G/800G Single Channel Ethernet PCS/FEC IP.

Tools, IP for GlobalFoundries
Cadence will develop IP for GlobalFoundries’ 12LP and 12LP+ FinFET platforms. The offerings will include DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5, as well as chiplet-based PHY IP and 16G multi-protocol SerDes. The first product on the GF 12LP platform is the 16G Multi-Link and Multi-Protocol PHY.

Additionally, Cadence uncorked a Mixed-Signal OpenAccess process design kit that supports GF’s 22FDX FD-SOI platform. The interoperable flow, which targets 5G mmWave, edge AI, IoT and automotive designs, uses the Cadence digital full flow and custom and RF platforms.

Synopsys will develop a portfolio of IP for GlobalFoundries’ 12LP+ FinFET process, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP.

Synopsys’ Fusion Compiler RTL-to GDSII product has also been optimized for GlobalFoundries’ 12LP and 12LP+ FinFET platforms and 22FDX FD-SOI platforms, with improved PPA and FD-SOI specific adaptive-body biasing (ABB) and forward-biasing design flows.

Mentor and GlobalFoundries released a design for manufacturability (DFM) kit that includes machine learning capabilities. Built on Mentor’s Calibre nmDRC platform, the DFM kit aims to find new and previously unseen hotspot patterns and improve production yield. It is launching as an update to the PDK for GF’s 12LP+ platform, with 12LP and 22FDX expected later in the year.

Analog Bits uncorked a library of foundation analog IP portfolio for GlobalFoundries’ 12LP FinFET and 12LP+ platforms, including  integer and Fractional Phase-Lock Loop (PLL), ring oscillator based PCIe 2/3 PLL, Process Voltage and Temperature (PVT) sensors, and Power on Reset (POR) circuitry and LC oscillator based PCIe 4/5 PLL for 12LP+.

Efabless expanded support for GlobalFoundries’ 130G solution. Efabless’ offering includes digital design and low cost ASIC development based on configurable design templates with cloud-based access to EDA tools, infrastructure, and prototyping services. The initial SoC design template for GF130G includes an Arm Cortex M0 processor and a selection of analog and digital peripherals and targets applications such as IoT controllers.

Deals
SemiDrive adopted Arteris IP’s FlexNoC interconnect IP and the accompanying Resilience Package as the on-chip communications backbone for its ISO 26262-compliant smart e-cockpit, central gateway, autonomous driving and ADAS chips. SemiDrive cited the ability to optimize bandwidth, latency and power consumption to meet the real time requirements of autonomous driving.

The University of Texas at Arlington (UTA) and Ansys are teaming up on a design and analysis workflow for validating system models in the U.S. government’s current and next-generation hypersonic vehicles. Ansys will simulate aspects such as design and analysis of air and fuel mixing inside a scramjet to measuring the impact of thermal stresses on vehicle sensors, while UTA will verify the software code’s accuracy by conducting physical high-speed flight tests in UTA’s arc jet hypersonic wind tunnel.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

DesignCon is hosting a free ‘Back to School’ webinar series Sept. 28-Oct. 2. Topics will include beginning RF & microwave PCB design, open signal integrity tools, 112-Gb channel modeling, power connectors, and PCB material characterization. In addition, DesignCon will move to the San Jose Convention Center for its conference next year, slated for April 13-15 2021. The conference will be expanding to include features on automotive electronics/intelligence and IoT.

The AI Hardware Summit virtual event will take place Sept. 29-Oct. 7 with a focus on optimizing systems for AI and machine learning, including co-design, edge applications, and the impact of AI on memory, storage, and networking.

VSDOpen, a virtual event dedicated to open source EDA and designs, will take place Oct. 10 with workshops available Oct. 7-9. Topics will include RISC-V in India, open IP designs, and what can be learned from the open source software movement.



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