Week in Review: Design, Low Power

Intel reports quantum breakthrough; Samsung Foundry certifies EDA tools; Synopsys tackles ECO; Renesas inks wireless partnership; Arm licenses virtualization tech.


Could power beams be the key to smart city infrastructure and 5G/6G connectivity? A new report says both lasers and microwaves offer possible paths forward in this area, though both technologies come with benefits and drawbacks.

Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they’re expected to do, and how quickly they’re supposed to do it.


Intel achieved what it described as a “major milestone” in scaling and fabricating quantum computing chips. The company’s Oregon-based transistor research and development isolated 12 quantum dots and four sensors using Intel’s cryoprober and second-generation silicon spin test chip. The company said the result “represents the industry’s largest silicon electron spin device with a single electron in each location across an entire 300 millimeter silicon wafer.”

Startup funding hit over $2.9B in September, including funding for quantum computing, EDA, power, energy harvesting, and more.

Tools, Products, & Deals

Multiple companies announced certifications from Samsung Foundry this week as Samsung unveiled its plan to triple advanced chip production by 2027, among other goals. The list of certifications includes SiemensCalibre nmPlatform on the foundry’s 3nm process technology, Siemens’ Aprisa digital implementation tool for the foundry’s 4nm finFET technology node, Cadence‘s Voltus-XFi power integrity tool on the foundry’s 5LPE process technology, Cadence’s RFIC design reference flow on 8nm process technology, and “multiple successful test chip tapeouts on Synopsys digital and custom design tools and flows” for the foundry’s 3nm technology.

Synopsys also introduced an engineering change order (ECO) tool called PrimeClosure aimed at speeding up chip design closure in HPC, AI, automotive, and mobile designs on advanced process technologies. “Scaling productivity in hyper-convergent designs requires innovative solutions that can quickly and efficiently optimize PPA targets in very large design spaces,” said Jacob Avidan, senior vice president of engineering for the Silicon Realization Group at Synopsys. Additionally, Synopsys said this week it added IntelliJ support for its Code Site Standard Edition security application. Jason Schmitt, general manager of the Synopsys Software Integrity Group, said giving developers technology that “helps them write more secure code seamlessly in their IDE is not only effective at reducing software risk, but it alleviates the costly burden of finding and fixing security vulnerabilities in the later stages of the SDLC.”

Renesas announced a strategic partnership with Jariet Technologies aimed at expanding Renesas’ portfolio of wireless transceiver products. The terms of the collaboration include Renesas investing $7 million in Jariet’s new funding round. “Gaining access to Jariet’s expansive analog and mixed-signal technology expertise will allow us to field RF front-end reference designs that meet the future requirements of 5G wireless infrastructure and high-performance Satcom applications,” said Sailesh Chittipeddi, executive vice president and general manager of the IoT and Infrastructure Business Unit at Renesas.

Arm licensed Corellium‘s virtualization technology as part of Arm’s virtual hardware offerings. “We are committed to simplifying IoT development and enabling software and hardware co-design,” said Mohamed Awad, vice president of IoT and Embedded at Arm. “Through our partnership with Corellium, we have been able to rapidly expand Arm Virtual Hardware – an entirely new way for software developers to innovate and accelerate product design for diverse IoT devices, all in the cloud.”

Upcoming events

Oct. 3-21, Samsung Foundry Forum & SAFE Forum, San Jose, EMEA, Japan, Korea, China

Oct. 19-21, Electronic Specialty Gas Conference, Chandler, AZ

Oct. 20-11, IEEE ISICAS: International Symposium on Integrated Circuits, Bordeaux, France

Oct. 24-28, Hardwear.io Security Trainings and Conference, The Hague, Netherlands

Oct. 25-27, PAINE: Physical Assurance & Inspection of Electronics, Huntsville, AL

Oct. 26-27, Arm DevSummit, San Francisco, CA   

Find more chip industry events here.

In case you missed it

Check out the Systems & Design newsletter and the Low Power – High Performance newsletter for these highlights and more:

  • Strengthening The Global Semi Supply Chain
  • Designing For Thermal
  • Can ML Help Verification? Maybe
  • Rethinking Machine Learning For Power

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