Week In Review: Design, Low Power

Image signal processors; authenticating USB devices; auto-grade NOR.


Arm debuted two new image signal processors, Mali-C52 and Mali-C32. Both are capable of processing for high dynamic range (HDR), noise reduction, and color management at 4k resolution at 60fps. They can process 600 megapixels/sec. The Mali-C52 can be configured either for image quality or area for a range of applications, while the C32 is optimized for area and lower-power, cost-sensitive applications. Along with the ISP hardware IP, Arm provides software drivers and calibration and tuning tools.

USB-IF launched a cryptographic-based authentication program for USB Type-C devices and chargers. The specification allows host systems to protect against non-compliant USB chargers and to mitigate risks from malicious firmware/hardware in USB devices attempting to exploit a USB connection. It works before inappropriate power or data can be transferred. DigiCert will manage the PKI and certificate authority services.

SST’s high-speed embedded NOR SuperFlash technology was qualified to AEC-Q100 Grade 1 on UMC’s 55 nm platform. Endurance testing for the automotive qualification included 700,000 program/erase cycles and 20 years of data retention.

CEVA won a number of deals for its Bluetooth Dual Mode IP: Bestechnic incorporated it into an audio SoC targeting high-end headphones and headsets, and Optek used it in a multimedia SoC for AI, voice and music applications such as hearables and wireless speakers. Meanwhile, InPlay Technologies deployed Bluetooth Low Energy IP in a radio SoC targeting various low power wireless applications including wearables and health. Additionally, Nordic Semiconductor licensed CEVA’s DSP in a multimode LTE-M/NB-IoT SoC for low power cellular IoT connectivity.

There’s still time to participate in the OneSpin Holiday Puzzle. This year’s challenge asks designers to improve on a digital circuit that calculates Fibonacci numbers, a familiar sequence that adds the two previous numbers (0, 1, 1, 2, 3, 5, 8…), to make it faster and simpler. The deadline for submission is Jan. 13.

DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs. Advanced registration rates close Jan. 28.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.

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