Week In Review: Design, Low Power

Synopsys unveiled the latest version of its IC Compiler II place-and-route system, adding a common physical optimization infrastructure, new arc-based unified concurrent clock-and-data (CCD) optimization, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. Additionally, next-generation distributed parallelization, intelligent scenario management, efficient infrastructure scaling, and inherent core engine algorithm acceleration are implemented, and the company says the tool achieves 2X faster throughput, 10% power reduction, 5% smaller area, and 5% better timing. Realtek noted it has adopted the tool.

The RISC-V base ISA and privileged architecture specifications have been ratified by the RISC-V Foundation. “Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever,” said Krste Asanović, chairman of the RISC-V Foundation Board of Directors, even as the architecture evolves through the development of new extensions. Additionally, the RISC-V privileged architecture covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices. Each privilege level has a core set of privileged ISA extensions with optional extensions and variants, including the machine ISA, supervisor ISA and hypervisor ISA.

EDA and IP revenue were back up again in Q1 2019, with an increase of 16.3% to $2.606 billion, the ESD Alliance reports. All EDA sectors plus IP showed gains of 18.8% and 14.8% respectively, with services revenue falling 3.9%. Using a four-quarter moving average, which is a better measure of industry health, worldwide growth rose 6.1% to $2.463 billion in the first quarter, up from $2.322 billion in Q1 2018. “What isn’t in the report is that license and maintenance revenue was up 18.3%, which is the largest growth ever in a quarter,” said Wally Rhines, CEO emeritus at Mentor, a Siemens Business, and member of the ESD Alliance Governing Council. Employment in the industry is still rising as well, up 5.8% to 43,500 professionals from Q1 2018 and 1.7% from Q4 2018.

Bitmain licensed Arteris IP’s Ncore Cache Coherent Interconnect IP for use in its next-generation Sophon Tensor Processing Unit (TPU) SoCs for scalable hardware acceleration of AI and machine learning algorithms. Bitmain cited the ability to increase on-chip bandwidth and reduce die area using the IP, as well as ease of implementation in the backend.

The MOSIS Service selected Synopsys’ IC Validator tool for physical verification signoff, including full-chip design rule checking and layout-versus-schematic signoff on designs in FinFET process technologies on its multi-project wafers. MOSIS cited the tools productivity and performance functionality to sign off designs on-time.

Graphics IP company Think Silicon announced a seed funding round led by Metavallon VC. Based in Greece, Think Silicon specializes in ultra-low power consumption GPUs, display controllers, and machine learning accelerators for battery-powered display and vision devices. The company also plans to expand into higher graphics performance segments.