Week In Review: Design, Low Power

Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 million in both cash and the assumption of debt.

Cadence completed the acquisition of the AWR business unit from National Instruments for about $160 million in cash. AWR’s focus is high-frequency RF design automation tools, particularly in the millimeter wave and microwave spectrums, which are critical for radar and 5G.

Tools & Standards
MathWorks HDL Verifier now supports UVM. HDL Verifier enables design verification engineers developing FPGA and ASIC designs to generate UVM components and test benches directly from Simulink models and use them in simulators that support UVM. New features include generation of UVM components, SystemVerilog assertions, and SystemVerilog DPI components from MATLAB and Simulink.

MIPI I3C v1.1 has been published. I3C is a scalable, medium-speed, utility and control bus that connects peripherals to an application processor and aims to address historical pain points of I2C development. MIPI I3C integrates mechanical, motion, biometric, environmental and any other type of sensor. Updates in v1.1 include features for peripheral command, control and communication to a host processor over a short distance, including extensible use of extra bus lanes to increase the interface speed to near 100 MHz. “As we look at the next evolution of MIPI I3C, the working group will be considering a range of new capabilities, including longer reach, various specification development improvements, more automotive requirements, speed increases, new multi-lane uses, new PHY approaches, standardized connectors and other feature refinements,” said Ken Foust, MIPI I3C Working Group chair.

JEDEC updated the LPDDR5 standard. JESD209-5A, Low Power Double Data Rate 5, will eventually operate at an I/O rate of 6400 MT/s, 50% higher than that of the first version of LPDDR4, and will significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. This update to the LPDDR5 standard is focused on improving performance, power and flexibility. Additional timing parameters and minor editorial corrections have also been included.

Broadcom will continue to use Cadence’s digital implementation solutions in the creation of its 5nm designs, following a successful collaboration between the companies at 7nm.

Synopsys joined the new Autonomous Vehicle Computing Consortium, a group of companies in the automotive, semiconductor, and computing industries aiming to accelerate the delivery of safer and affordable vehicles. Synopsys will actively contribute to the development of a set of recommendations for system architectures and computing platforms that will be used to address the challenges of deploying self-driving vehicles at scale.

Events
Check out upcoming industry events and conferences: DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design. FPGA 2020 will be held Feb. 23-25 in Seaside, CA, and includes sessions on deep learning, architectures, tools, and security. Plus, DAC submissions for the Designer and IP Track are open through Jan. 22, 2020 and nominations for the Marie R. Pistilli Women in EDA award are open; the conference will be co-located with SEMICon West July 19-23, 2020 in San Francisco, CA.