tag: LPDDR5

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)
By Technical Paper Link - 13 Sep, 2023 - Comments: 0

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

LPDDR5X: High Bandwidth, Power Efficient Performance For Mobile & Beyond
By Vinitha Seevaratnam - 08 Jun, 2023 - Comments: 0

Looking back over recent history in the memory landscape, we can clearly see a trend of new applications growing sufficiently large enough to command the creation of new memory technologies tailored to their specific needs. We saw this with the creation of GDDR for graphics and later HBM for AI/ML applications. Low-Power Double Data Rate (LPDDR) emerged as a specialized memory designed for mobi... » read more

Shifting Auto Architectures
By Ed Sperling - 29 Apr, 2021 - Comments: 0

Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

Forward And Backward Compatibility In IC Designs
By Ann Mutschler - 30 Nov, 2020 - Comments: 0

Future-proofing of designs is becoming more difficult due to the accelerating pace of innovation in architectures, end markets, and technologies such as AI and machine learning. Traditional approaches for maintaining market share and analyzing what should be in the next rev of a product are falling by the wayside. They are being replaced by best-guesses about market trends and a need to bala... » read more

LPDDR4/4X DRAM Variants and Possible System Configurations
By Synopsys - 26 Feb, 2020 - Comments: 0

LPDDR is the de-facto standard for main-memory targeting mobile applications such as smartphones and tablets. Low-Power Double Data Rate Synchronous Dynamic Random Access Memories (LPDDR SDRAMs) or DRAMS offer high-performance while consuming significantly lower power than standard DDR memories, such as DDR5/4/3, which are ideal for systems requiring large memory capacity. For this reason, LPDD... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Jan, 2020 - Comments: 0

Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 millio... » read more

Tricky Tradeoffs For LPDDR5
By Ann Mutschler - 30 Oct, 2019 - Comments: 0

LPDDR5 is slated as the next-gen memory for AI technology, autonomous driving, 5G networks, advanced displays, and leading-edge camera applications, and it is expected to compete with GDDR6 for these applications. But like all next-gen applications, balancing power, performance, and area concerns against new technology options is not straightforward. These are interesting times in the memory... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Advantages Of LPDDR5: A New Clocking Scheme
By Brett Murdock - 05 Sep, 2019 - Comments: 5

Earlier this year, JEDEC released the new standard, JESD209–5, Low Power Double Data Rate 5 (LPDDR5). Those that contributed to the development of the standard come from a diverse technology background and represent both manufacturers and consumers of SDRAM memories. Now we have a new memory standard to help enable the future that requires more compute power, higher reliability, and lower pow... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Mar, 2019 - Comments: 0

Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

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