The Week In Review: Design/IoT

NXP acquires BTLE team from Quintic; Cadence unveils Stratus HLS; Synopsys launches open-source suite for ARC; ARM reveals mbed IoT starter kit; Si2 adds two SPICE standards; Mentor & Ansys financial results.

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Mergers & Acquisitions

NXP acquired Quintic’s Bluetooth Low Energy and Wearable businesses, adding BLTE to their low power RF-connectivity portfolio. The team of approximately 65 is expected to join NXP when the deal closes in Q1 2015.

Tools

Cadence unveiled the integration of Forte’s Cynthesizer with their own C-to-Silicon Compiler. The result is the Stratus high-level synthesis platform, designed to be utilized across an entire SoC design.

IP

Synopsys launched the embARC Open Software Platform, providing online access to a suite of free and open-source software for developing embedded systems based on DesignWare ARC processors.

Chips

NXP brought out two new microcontroller families (LPC18Sxx and LPC43Sxx) to help embedded developers secure application code and data messages in connected applications. They also released a new contact smart card interface, TDA8037, designed for pay-TV applications.

Standards

Si2’s Compact Model Coalition added two new SPICE model standards for FDSOI MOSFETs based on the UC Berkeley Shortchannel IGFET Model (BSIM) and on the Hiroshima University STARC IGFET Model (HiSIM) compact model platforms.

Deals

ARM revealed the mbed IoT Starter Kit. The kit includes an mbed development board from Freescale hosting a Cortex-M4 based processor and Ethernet connectivity to hook up with IBM’s Bluemix cloud platform.

Hitachi utilized Cadence’s Virtuoso AMS Designer to reduce the verification time for a new backplane signal conditioner mixed-signal chip. Hitachi presented a paper on this design and their use of Virtuoso AMS Designer and RNM at ISSCC 2015.

Texas Instruments implemented Arteris’ FlexNoC interconnect fabric IP in its SimpleLink wireless MCU portfolio, focused on low-power devices that spend much of their time in idle modes.

eSilicon completed tape out of an SoC design using Sonic’s interconnect fabric, SonicsGN, as the interconnect fabric, citing design requirements for rapid IP integration and high bandwidth.

Brite Semiconductor used Cadence Encounter Digital Implementation System for physical implementation and Voltus IC Power Integrity Solution for power signoff and design closure to complete four 28nm SoC designs.

NXP partnered with Sonova, a manufacturer of hearing care products, to develop the Venture platform used in Sonova’s Phonak Audéo V hearing aids.

Cadence and Hillcrest Labs announced a port of Hillcrest’s Freespace always-on sensing software is now available for Cadence Tensilica DSPs.

Numbers

Mentor Graphics released fourth quarter and full year 2014 financials. Revenues were $439.1 million for Q4, up 9.5% from Q4 2013, with non-GAAP earnings per share of $1.09 ($0.96 GAAP). For the full fiscal year, revenues were $1.244 billion, up 7.6% from last year. Earnings per share were $1.77 on a non-GAAP basis ($1.26 GAAP).

Ansys also posted financial results for Q4 and full-year 2014. Fourth quarter GAAP revenue was $254.4 million with a non-GAAP revenue of $255.5 million, both up 8% from Q4 2013. For the whole year, 2014 GAAP revenue was $936.0 million and non-GAAP revenue was $941.4 million, both up 9% from 2013.

Benchmarks

Cadence’s multi-protocol SerDes PHY IP for PCIe 2.0 and PCIe 3.0 technology for TSMC’s 16nm FinFET Plus (16FF+) process passed PCI-SIG compliance testing.