The Week In Review: Design

PCB DFT; CNN engines; new EPU.



Mentor released new software for automated set-up of PCB DFT rules. The tool extracts relevant PCB design technology from the design data to determine the correct PCB technology classification, then maps the PCB classification to the constraints associated with the applicable manufacturing processes to run only the checks necessary for the design.


Synopsys improved the convolutional neural network engine in its EV6x vision processors, providing uo to 4.5 TeraMACs per second on a 16nm finFET process and supports both coefficient and feature map compression/decompression to reduce data bandwidth requirements and decrease power consumption. It supports any CNN and delivers power efficiency of up to 2,000 GMACs/sec/W on 16nm finFET.

Sonics launched the latest in its line of energy processing units (EPU), adding the ability to automate implementation of dynamic voltage and frequency scaling (DVFS). ICE-P3, according to the company, identifies, sequences, and controls power state transitions in hardware up to 500X faster than conventional software-based approaches.

VeriSilicon uncorked a family of IP based on a highly parallel, scalable MESH (Memory Efficient Shader) processor architecture. It supports complex math instructions and double precision operation, says the company. The CC8400 variety has 256 MESH cores, each with a 32-bit single-precision compute unit which delivers 576 GFLOPS of compute performance at clock rate of 1GHz. The cores are OpenCL 1.2 FP and OpenVX compliant.


Kyocera selected Synopsys’ VC Formal for formal property verification of their Multi-Functional Product SoC designs used in printers.

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