The Week In Review: System-Level Design

Synopsys cuts the power on NVM IP; Cadence boosts RTL synthesis; Mentor posts solid quarter; ARM wins deal for ultra-HD TV chips.


Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs.

Mentor Graphics posted positive numbers across the board for its fiscal Q3 ended Oct. 31. Revenue was $275.6 million, up from $268.8 million in the same period in 2012. Net income was $25.5 million, down slightly from the $30.6 million, but up slightly on a non-GAAP basis. The company cited physical verification, design for test, emulation and automotive applications as some of the key drivers for the quarter. Mentor also announced a dividend of 45 cents per share.

Mentor also won a deal with Digital Media Professionals, which will use its verification platform for graphics IP. DMP develops high-performance algorithms for 2D vector and 3D graphics.

Cadence added new capabilities to its RTL synthesis technology, which it says improves performance, power and area by up to 15% for complex chips that are encountering timing or congestion challenges. Cadence also highlighted the successes of some of its customers. Faraday completed a 300 million-gate design for a 4G base station all the way to takeout in seven months using Cadence’s digital flow. Tilera, meanwhile, reduced the time it took to reach power signoff from 65 to 8 hours for dynamic analysis of a 72-core SoC design, and sliced static analysis from 12 to 2.5 hours.

ARM won a deal with Amlogic, which rolled out an ultra-HD SoC based on a six-core ARM GPU and a quad-core CPU. Amlogic is targeting the chip at high-end digital TVs, set-top boxes and smart IP TVs.

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