The idea of distinct nodes will become less useful as time goes on.
The idea of clearly defined “technology nodes” has been more theoretical than practical for quite some time now. Electrostatic and power consumption considerations have long made it difficult to scale transistor dimensions at the same rate as memory density. Meanwhile, lithography has become more and more challenging, particularly for the arbitrary patterns commonly seen in logic design.
As An Steegen, IMEC’s senior VP for process technology, explained in her presentation at last week’s IMEC Technology Forum, the technology node concept will be less and less useful as time goes on. While metal pitch at the 5nm node is likely to be about a quarter of 20nm node metal pitch, the corresponding contacted polysilicon (gate) pitch will be more like one-third of its 20nm node value. Moreover, there is likely to be substantial divergence among manufacturers, with as much as 20 nm of variation in gate pitch within a single “node.”
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Image courtesy of IMEC.
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