What Is Electronic Design Automation And Why Do You Need It?

As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible. Traditional design tools and practices can result in failed prototypes, costly respins, delayed time-to-market, missed market opportunities, and subpar performance.

This is why advanced EDA tools are no longer optional. They are critical for successfully navigating the complexities of modern high-speed digital design and delivering competitive products on time and within budget.

So, what is EDA, and why do you need it? What are the challenges of high-speed digital design? How do advanced EDA tools address those challenges? Keep reading for the answers.

What is EDA?

Fig. 1: Iterative EDA workflow.

Electronic design automation software streamlines the design process, simulation, and validation of electronic circuits and systems.

These electronic computer-aided design (ECAD) tools automate common tasks like schematic capture, simulations, layout, rule checks, and verification to reduce engineering effort and avoid errors.

The philosophy of EDA is “shift left.” All design checks must be done as early as possible (i.e., toward the left on a timeline) to avoid expensive prototyping runs and respins later. Shift left requires the ability to analyze and predict complex behaviors using just the virtual circuit schematics, virtual layouts, software models, and simulators.

EDA and electronic simulations are essential for the design of reliable high-speed digital systems.

What is electronic simulation?

Fig. 2: Digital twins enable sophisticated simulations in the shift left paradigm.

Simulation tools create virtual models (digital twins) of circuits, subsystems, or electronic systems for emulation of real-world phenomena under different conditions.

Some common types include circuit-level, electromagnetic (EM), electro-thermal, and system simulations.

What specific challenges in HSD electronics design do EDA tools address?

High-speed digital signals typically ride upon high-frequency (HF) analog signals whose complex effects must be modeled, predicted, simulated, and mitigated as early as possible to avoid costly prototyping runs and respins. This is where EDA tools help.

Let’s examine key high-speed digital challenges in more detail.

Signal integrity challenges

Wires and traces of high-speed digital circuits act like transmission lines and affect signals. EDA tools must ensure signal integrity by modeling and mitigating adverse effects like the following:

• Attenuation: HF multi-gigabit signals undergo significant attenuation and dispersion losses in channels and interconnects. Integrating equalization circuits into the design is essential to compensate for these losses.
• Reflections: Impedance mismatches and discontinuities in traces, vias, and connectors cause signal reflections. Proper impedance matching and controlled impedance transmission lines are crucial.
• Crosstalk: Electromagnetic coupling between traces can lead to interference. Minimizing crosstalk is crucial, especially at higher operating frequencies.
• Jitter: All the digital standards demand very low jitter. For example, the double data rate (DDR5) standards impose very low margins of tolerance on random jitter.
• Inter-symbol interference (ISI): This is due to channel impairments and requires equalization.
• Parasitic effects: Parasitic capacitance, resistance, and inductance significantly impact signal integrity.
• Channel effects: High-frequency effects create major signal degradation problems in the serial and parallel buses of telecommunications and computer systems.

Power integrity challenges

The power delivery network (PDN) is a critical subsystem of digital ICs and PCB layouts. It ensures that all other subsystems and components reliably receive the required voltage and current with minimal impairments.

Ideal power integrity has these key goals:

• Minimize the direct current (DC) voltage drops (also called DC IR drops) due to resistance in the power and ground planes.
• Maintain clean power delivery to the load to meet voltage and ripple specifications.
• Ensure that PDN impedance is flat from DC to the highest-frequency components.
• Identify power rail impedance peaks in the frequency domain to predict worst-case transients.
• Pay attention to simultaneous switching noise because it affects signal integrity as well.
• Avoid transient noise. Power-saving modes and data bursts create fast transients and voltage noise ripples.

Electromagnetic interference and compatibility challenges

Reducing electromagnetic interference (EMI) and maximizing electromagnetic compatibility (EMC) are mandatory in automotive, avionics, consumer electronics, and the industrial internet-of-things (IoT) ecosystem. Their designers face challenges when implementing requirements such as:

• Design all subsystems and packaging with proper shielding and grounding.
• Minimize radiated emissions.
• Predict and mitigate all potential EMI noise sources early in the design phase.
• Analyze conducted EMI to meet EMC requirements.
• Reduce the output swing to reduce crosstalk and EMI noise levels.

Timing challenges

Clock and data recovery (CDR), timing, and synchronization are critical HSD aspects. Some challenging aspects to address include:

• ensuring proper clock signal distribution
• minimizing clock skew
• meeting stringent timing budgets
• verifying that all clocked elements meet setup, hold time, and jitter requirements

Standards compliance challenges

High-speed serializer-deserializer (SerDes) digital systems must adhere to relevant specifications including:

• Ethernet standards like 802.3dj for data center networks or 802.3cy for automotive networks
• Memory standards like DDR5 or LPDDR5
• Peripheral Component Interface Express (PCIe) 5.0 and 6.0 standards
• Universal Serial Bus (USB) standards like USB4
• Consumer electronics standards like MIPI and high-definition multimedia interface
• Universal Chiplet Interconnect Express (UCIe) for chiplets
• MIL-STD-461F standard for EMI and EMC in defense systems

All these standards have stringent requirements on signal quality, eye mask compliance, jitter budgets, and other aspects.

Since failed compliance tests can be expensive, it’s crucial to simulate and analyze such aspects directly on the virtual prototypes.

Thermal challenges

More components packed in small spaces lead to higher power densities, increased temperatures, and heat dissipation problems.

Additionally, managing heat dissipation depends on material properties, component density, placement, and other conditions.

In ICs, advances like the gate-all-around transistor create new heat dissipation problems.

In all these cases, it’s critical to know how the heat flows due to radiation, convection, and conduction effects.

Semiconductor design challenges

Fig. 3: Traditional SoC design vs. chiplet-based design.

Increasing integration as SoCs or 2.5D/3D chiplet designs and increasingly dense packaging result in complex electromagnetic coupling effects.

Ensuring that chiplet die-to-die (D2D) interconnects are interoperable and work reliably is challenging.

PCB design challenges

Modern PCBs are increasingly complex and multi-layered. Designers need to verify every aspect of layout geometry to avoid crosstalk and losses. We can get an idea of PCB complexity based on the fact that some computer motherboards even back in 2018 already had as many as 32 layers, 8,000 nets, and 12,000 components.

Datasheet limitations

Datasheets often fail to reveal worst-case voltage noise ripple for fast PDNs. Traditional step-load transient tests used in datasheets may not uncover resonant frequencies or forced responses that cause larger voltage ripples.

Engineering and organizational challenges

Common engineering, organizational, and process challenges are outlined below:

• Specialized EDA tools from different vendors are needed, but they don’t integrate well with each other. Manual data transfers, conversions, and processing are often needed to make them interoperate.
• Correlating the simulation outputs with measured results from tests done on physical designs can be time-consuming.
• Time-to-market pressures demand shorter design cycles and efficient design flows.
• Complex simulations require significant computational resources and configuration effort.
• Designs must meet many legal, regulatory, and safety requirements.
• Product complexity is growing at a much faster rate than the experienced engineering workforce.

Enabling superior high-speed digital designs

Fig. 4: Signal integrity using Keysight ADS.

Mainstream EDA software provides some features to simulate the designs of both high-speed digital ICs and PCBs. We have described the high-level EDA workflows for IC and PCB designs before.

However, they have several limitations. For example, traditional simulators fail at HSD designs because their input/output circuits are too complex and their design space is too large. For logic blocks of 10,000-50,000 transistors, they can take hours to days to provide useful results.

Keysight’s Advanced Design System (ADS) platform and its EDA tools fill such crucial capability and productivity gaps in the design workflows for high-speed digital systems. Let’s review these capabilities in depth below.

Advanced electromagnetic modeling

The PathWave EM Design (EMPro) enables advanced EM-circuit co-simulations. Its capabilities include the following:

• Predict 3D electromagnetic effects across an entire device with chips, packaging, interconnects, shielding, PCB, and connectors.
• Support finite element method and finite difference time domain (FDTD) simulation techniques.
• Support EMC and EMI analyses using FDTD.
• Simulate radiated emissions to determine compliance with EMC standards.
• Support both pre-layout and post-layout EM verification.
• Simulate designs in both the time and frequency domains.
• Allow interactive analysis of EM effects in complex designs.

Signal integrity

Keysight ADS for high-speed digital design enables signal integrity simulations and analyses for complex high-speed PCBs. It can:

• synchronize signal integrity simulations automatically with every change in the circuit design, layout, and routing
• simulate attenuation and dispersion losses
• identify potential crosstalk elements and coupling in signal and power nets
• conduct transient and channel simulations
• enable accurate transmission line modeling using the Controlled Impedance Line Designer
• detect impedance mismatches, return path discontinuities, and via stub resonances
• conduct jitter separation analysis to identify and mitigate jitter sources
• simulate serial and parallel buses using the channel simulator and bus simulator that allow rapid signal integrity analysis and produce ultralow bit error rate (BER) contours quickly using statistical analysis
• simulate using built-in generic models as well as IC models that conform with the input/output buffer information specification (IBIS) standard
• account for ISI, random jitter, encoding, and equalization

Power integrity

Fig. 5: Power integrity analysis.

ADS supports comprehensive simulation and analyses of PDNs. Its features include the following:

• PIPro supports power integrity analysis of PDNs, including DC voltage drop analysis, impedance analysis, and power plane resonance analysis.
• PIPro’s EM algorithms are more efficient and faster than general-purpose EM tools. PIPro can analyze the impedance of a PDN, simulate Z-parameters, optimize impedance in the frequency domain, and design for flat impedance across frequencies to minimize capacitors and reduce resonances.
• PIPro supports PDN transient simulations, simulations of cascaded and parallel power conversion topologies, and power rail simulations.
• The Power Integrity Designer can simulate designs that deliver thousands of amps to the next generation of custom multi-die packages, artificial intelligence (AI) chips, and cloud server applications.

Electro-thermal analysis

Fig. 6: Electro-thermal analysis.

The Electro-Thermal Simulator supports temperature-aware circuit co-simulation across boundaries (IC, package, laminate, and PCB) of high-speed digital PCBs and ICs.

The Electro-Thermal Dynamic Model Generator creates time-varying electro-thermal models to speed up thermal simulations.

IC design, chiplets, and UCIe

Fig. 7: Chiplet PHY Designer.

Keysight provides advanced EDA tools to semiconductor companies for chip design, chiplets, and interconnects:

• The Chiplet PHY Designer supports simulation UCIe, system-level analysis of die-to-die (D2D) PHY links, and jitter tracking.
• The IC-CAP device modeling software and DynaFET model can simulate phenomena like dynamic self-heating and trapping effects. AI and machine learning (ML) algorithms in IC-CAP enable full automation of the model recentering process, accelerating it by 10x from days to hours.
• ADS supports the advanced multi-physics analyses of 2.5D/3D ICs to accurately capture coupling effects.

SerDes designs

IBIS and the algorithmic modeling interface (AMI) enable the creation of SerDes behavioral models that can simulate functions like equalization and CDR of multi-gigabit channels.

Data center Ethernet and optical networks

The Ethernet AMI Modeler can create AMI models for Ethernet transmitters and receivers, including support for PAM4 modulation.

Keysight SystemVue provides an optical fiber communication library that can create a model of a rack-to-rack optoelectronic link and export it to the ADS Channel Simulator.

PCIe and USB features

System Designer for PCIe enables designers to perform complete PCIe system analysis and simulation-driven virtual compliance tests with a streamlined workflow.

PCIe AMI Model Builder and USB AMI Modeler generate AMI models to simulate features like equalization and CDR of PCIe and USB transmitters and receivers.

Memory designs

The ADS Memory Designer supports the design of various memory systems that comply with DDR, graphical DDR (GDDR), or high-bandwidth memory (HBM) standards. It supports channel simulation of high-speed serial channels and memory systems with data bus or command address control buses.

Additionally, the DDR AMI Modeler can generate PAM4 AMI models for memory interfaces.

System design and simulations

SystemVue can simulate entire devices consisting of many electronic subsystems. It can import different types of models like semiconductor device models and SerDes IBIS-AMI models. It can simulate all the subsystems together according to system-level requirements and orchestrate their signals and operations.

AI/ML capabilities

Keysight EDA tools use AI/ML to achieve the following:

• Advanced nonlinear circuit models can be trained using artificial neural networks.
• ADS has built-in Python integration with AI frameworks like PyTorch to train and run custom EDA models.
• Data from simulators and measurement systems enable the creation of reliable training datasets for custom EDA ML models.
• The Memory Designer includes AI/ML‑driven simulators for worst-case scenarios and bit pattern generation.

High-performance computing for simulations

The Keysight Design Cloud enables design teams to run computationally intensive circuit, EM, electro-thermal, and system simulations in a scalable cloud environment for faster time-to-insight.

Seamless integration with test and measurement instruments

A major benefit of using Keysight ADS is its ability to integrate seamlessly with various instruments like oscilloscopes, BER testers, and logic analyzers for physical tests on design prototypes. Model parameters can be extracted from the measured data and input into the virtual models to improve simulation accuracy.

EDA software integration with other design tools and systems

Keysight’s specialized EDA tools are designed to integrate seamlessly into mainstream design workflows. Its integrations are explained below.

• Interoperability: Keysight EDA’s specialized signal integrity and power integrity tools embed seamlessly into third-party mainstream digital design flows. Keysight EDA tools can import and export files using interoperable formats like Gerber and IBIS-AMI to integrate easily anywhere in an existing design flow.
• Data and IP management: Keysight Design Data Management (SOS) enables the sharing of simulation results with product lifecycle management tools, version control, and project management systems. The platform integrates with other mainstream EDA tools to enhance team collaboration across the entire development cycle.

How does EDA software accelerate product development in the digital design field?

Keysight EDA software accelerates product development and time-to-insight in the following ways:

• Powerful simulations: Tools like circuit simulators, EM co-simulators, and high-speed channel simulators enable verification of all design aspects as early as possible using virtual prototypes. Designers can tweak parameters in real-time to explore the design space.
• High-accuracy modeling: Keysight EDA tools use very accurate device and board models. The EM field solvers and electro-thermal analyzers produce realistic results with very high accuracy.
• Faster time-to-insight: Simulation-driven analyses enable engineers to quickly explore the design space and balance trade-offs. Keysight EDA automates standards compliance checks and provides guided workflows for designers.
• First-pass success: Simulations and analyses ensure that designs meet specifications and standards in the first design iteration itself. Early detection reduces the need for many hardware prototypes.
• Streamlined collaboration: Keysight data and IP management solutions keep all geographically distributed teams on the same page using centralized design data storage and optimal data synchronization. They can share schematics, simulation results, and intellectual property across teams.
• End-to-end workflows: Keysight EDA streamlines the entire digital design process, enabling seamless integration from concept to end of life. By automating complex tasks like design verification, simulation, and layout optimization, it reduces errors, shortens development cycles, and boosts efficiency. Keysight EDA also fosters collaboration between teams and ensures consistency across workflows, ultimately accelerating innovation and prototype development.

Solve high-speed digital complexity

In this blog, you learned about the technical and engineering challenges facing high-speed digital design teams. Keysight’s EDA solutions enable them to manage these challenges effectively.