When Things Go Wrong Even When You’re Doing the Right Thing

By Kurt Takara and Joe Hupcey III

“Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low power verification tools can’t tell me what’s going on!”

If you’ve ever found yourself muttering something like this on the way to another late night of espresso fueled troubleshooting, you’re not alone. Anyone involved in cutting-edge low power design has been flummoxed by thorny, new clock domain crossing (CDC) issues, in particular, metastability introduced by isolation and retention cells and new (and unexpected) asynchronous clock relationships created by voltage domains and power switches.

Figure 1: An isolation cell introduces a CDC path between synchronous registers — not good!

Fortunately, the next-generation of power aware CDC verification methodologies and tools can help resolve these CDC issues by employing netlist analysis, assertions, and formal verification. Questa “Power Aware” CDC helps engineers understand the impact of adding low power logic on top of multi-clock logic by automating:

• Low power-based clock and reset analysis
• Identification of low-power CDC paths and synchronization structures
• Identification of voltage domain crossing (VDC) paths and synchronization structures

What’s required here are both static and dynamic verification of CDC paths. Static techniques include identification of low power CDC paths and synchronization structures as well as support for both isolation and retention cell verification.

Static and dynamic approaches
Static structural analysis is used to identify both correct and incorrect CDC and voltage domain crossing (VDC) synchronization structures. That includes partitioning synchronous clock groups on different voltage domains into asynchronous clock groups. The addition of voltage domains in low power designs requires adding synchronizers on paths between variable voltage domains. This helps flag CDC violations on VDC paths that do not contain synchronizers. Both isolation and retention cells need to be reviewed to ensure that incorrect CDC paths are fixed and that isolation and retention cells do not disrupt correct CDC structures and do not introduce new CDC paths.

Also required are dynamic techniques that can leverage both simulation and formal model checking technologies on CDC protocol assertions and metastability delay models. CDC protocol assertions and metastability delay models can be generated for use with the dynamic CDC verification techniques in order to identify correct synchronization structures. Dynamic CDC verification involves verifying both CDC protocols and reconvergence logic. Each CDC synchronization structure type requires that the design logic adheres to a structure-specific set of protocols. During static structural CDC analysis, both CDC protocol assertions and metastability delay models can be generated for each type of synchronization structure. Finally, the CDC protocol assertions can be used to check the synchronizer-specific rules in simulation or static timing analysis.

Metastability delay models
These kinds of models can be generated for each CDC path. The metastability delays occur in silicon, but RTL simulation does not have the accuracy to model this behavior; so these models have to be added to the RTL simulation. The models can be used to monitor the CDC path for conditions that would cause metastability in silicon. When metastability conditions are discovered, the delay model either randomly adds a cycle of delay at the RX register for setup violations or subtracts a cycle of delay at the RX register for hold violations. Using metastability models ensures that each design is able to tolerate the metastability delays found in the design silicon.

Questa Power Aware CDC supports the latest generations of the Unified Power Format (UPF). UPF 2.0 and UPF 2.1 introduce successive refinement, which is a new concept for low power design and verification. Successive refinement supports the System-on-Chip (SoC) design and verification flow by allowing the UPF file to be refined and updated as it travels from block-design to SoC-design to SoC place and route.

One example of the successive refinement methodology in UPF 2.1 is that a power distribution network can be incrementally built over the duration of a project cycle by the different teams. The block and system designers can begin to verify the power management logic before the power distribution network has been implemented, with the final power management logic verification occurring later in the design flow when the physical designers add the power distribution network.

All of these advances in CDC verification will help you understand why all of the right things you are doing to reduce power sometimes make your design do the wrong things. To learn more about the challenges and solutions briefly mentioned in this blog, please read the DVCon 2015 paper “Next-Generation Power Aware CDC Verification: What Have We Learned?”

Additionally, in this 4 minute video on the Verification Academy YouTube channel, you can hear Kurt Takara walk through the corresponding DVCon poster.