Which Glitch Is Which?

Glitch is a commonly used term in modern vernacular, used to identify unexpected problems in everything from the space race, web site down time, or a crash of your latest mobile phone app. In electronics design glitch has a more specific meaning, referring to unnecessary signal transitions in a combinational circuit. Eliminating this extra switching activity can save power consumption, especially important in today’s low power designs, and reduce the risk of functional errors.

For designers, identifying glitches and revealing the extra power they consume requires special attention to cell delays and wire delays. Glitches occur if signal timing within the paths of a combinational circuit are imbalanced, causing a race condition. With accurate delay information, tools can capture these glitches and measure the power consumption caused by the extra switching activity.

Capturing vectors for glitch power analysis
Zero-delay simulation and emulation are often used to create waveform vectors for power analysis. Cell and wire delays are not modeled, which speeds vector creation. All signal transitions, or toggles, occur at the clock edge and power calculations are performed. This approach works fine for average power analysis which computes power based on toggle count. For peak power and glitch power analysis, however, SDF timing and delay calculation are needed to accurately capture when and where a glitch transition happens. Figure 1 below shows an example simple circuit, comparing waveforms with and without SDF timing delays – only with delays do we reveal a glitch and enable glitch power analysis:

Figure 1 – Revealing glitches require SDF waveforms that accurately model cell and wire delays

For this reason – accuracy – full gate-level simulations with SDF timing are the vector of choice for block, subsystem, and SoC power analysis sign off. Creating vectors with this level of detail, however, is time consuming. Often these vectors are not available until later in the design process when only minor corrections and optimizations can be made. To enable earlier and more frequent analysis of time-based peak and glitch power, a new approach is needed for early and accurate vector generation.

STA-based activity delay shifting and glitch
Activity delay shifting technology starts with readily available zero-delay vectors from simulation (RTL or gate-level) and then shifts the waveform for each and every signal based on delay information provided by gate-level static timing analysis (STA). The resulting vectors provide the accuracy needed to identify glitches and glitch power much earlier in the design process, without waiting for full gate level SDF simulations to be available. Figure 2 shows an example waveform with delay shifting, including iterations for cell re-sizing and buffer insertion:

Figure 2 – STA-based Activity Delay Shifting and Glitch Analysis

What’s more, STA-based delay shifted activity can be quickly updated to show the impact these ECO design iterations have on power analysis without the need to re-simulate the original zero-delay vectors.

Early and accurate glitch power analysis
With the delay shifting approach, Synopsys’ PrimePower gate-level power analysis tool enables designers to analyze glitches and glitch power much earlier in the design process. Results from early engagements are already good, showing total power within 1% of gate-level SDF simulated results and glitch power estimates that accurately capture trends and the impact of glitch removal and power recovery. Because PrimePower delay shifted waveforms are based on golden delay information from PrimeTime static timing analysis technology, designers gain the insight they need to:

• Identify which nets have glitches and how many
• Filter data to understand the severity based on glitch duration and power consumption
• Remove glitches and recover power through ECO cell re-sizing and buffer insertion

So don’t wait until the end to find out which glitch is which. Analyze problems earlier with Synopsys PrimePower’s STA-based activity delay shifting and glitch power analysis.