Winning The Global Race For Semiconductor Technology With Virtual Fabrication

Simulating all of the processing that occurs when real wafers are built for thorough process testing and optimization.


Semiconductor process development is no easy task, with each generation of devices more difficult and expensive to create. Traditional cycles of build-and-test development are becoming obsolete, since they are too expensive and time-consuming for the most advanced processes.

The high cost of process development

Most chip designers developing new products rely on existing manufacturing processes, but someone had to create those processes to make the designs possible. Process development, as contrasted with new chip design, requires an entirely different set of engineers and skills. The goal is to create new semiconductor manufacturing processes that provide high yield while achieving the required device performance.

Fig. 1:  Advanced gate-all-around nanowire transistor device.

The traditional approach has been to build multiple test wafers to determine the ideal process for a given device. After one set of wafers is fabricated and analyzed, process steps are refined for another round of fabrication based upon insights from the previous round. Each new process generation is more sensitive to variation, due to smaller features sizes. Testing must account for features and parasitics that could be ignored in prior generations, adding yet more complexity and measurements. The cycle is repeated many times before the entire process flow can be finalized. The time and cost of such process development is increasingly impractical, especially for the most advanced technology nodes.

Testing virtual wafers instead of real wafers

Today, there is an alternative to this slow, expensive way of doing things. Virtual fabrication lets computers simulate all of the processing that occurs when real wafers are built. These virtual models allow semiconductor process engineers to test manufacturing equipment settings with far greater variation than is possible in a physical fab. Designers can simulate the entire process flow, running the equivalent of thousands of wafers in days instead of months. The designers can quickly see graphical animations to visualize process steps, modify process recipes and device geometries, and measure how these changes impact electrical behavior.

Fig. 2:  Graphical animation of semiconductor process steps during virtual fabrication.

Improving yield using statistics in virtual wafer fabrication

Because of the high volume of data generated, statistical analysis can provide greater confidence in the choice of process settings. Defects and random variations can be modeled in a virtual fab in a way that’s not possible in a real fab, letting developers test the sensitivity of the device structures to the unpredictable aspects of processing.

There are a few approaches to optimizing the process settings used in a new memory or logic fabrication sequence. The simplest case involves taking a single variable and exploring its effects. Critical dimensions (CDs), for example, establish the device feature sizes that ensure desired electrical performance. A particular dimension can be swept from low to high values; developers can then measure the effects of that range on device behaviors like threshold voltage. The interactions with intersecting process steps can also be tested.

But, in reality, this approach is not sufficient to study the complex web of interactions between process steps and the resulting structures. A second approach leverages Monte Carlo analysis, randomly varying a wide range of process and device parameters and calculating the resulting device geometry and performance. This data can be used to automatically identify the process and design settings needed to achieve yield and performance goals. It is an area where simulation shines, providing a useful way to test the interactions between many different processes.

Fig. 3:  Statistical experiments using virtual fabrication.

Virtual fabrication platform

SEMulator3D is a virtual fabrication platform created by Coventor, a Lam Research company. It allows the definition of all process steps, the modeling of devices, the collection of metrics, electrical and device analysis, the statistical analysis of results, and the visualization of process steps through graphical animation. It is used by major semiconductor companies, both for optimizing and scaling leading process nodes and for developing advanced new technologies like GAA (Gate-All-Around) transistors.

Fig. 4: Gate-all-around transistor visualization in SEMulator3D.

The ability to do this work virtually is the future of semiconductor process development. Virtual fabrication accelerates new process time-to-market by months, opening up market opportunities worth hundreds of millions of dollars for leading-edge semiconductor companies.

To learn more about virtual fabrication and how it is changing the future of semiconductor technology development, please download our white paper “Speeding Up Process Optimization with Virtual Fabrication”.

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