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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

RISC-V’s Increasing Influence
By Brian Bailey - 12 Jun, 2025 - Comments: 2

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary to move forward gradually. Computer architectures and software have followed in the footsteps of processors developed 80 years ago. They aimed to solve sequential, scalar arithmetic problems usin... » read more

The DAC Valuation
By Brian Bailey - 29 May, 2025 - Comments: 2

The Design Automation Conference is approaching fast, and the evidence of a funding gap is in plain sight. An entire day of the technical conference has been dropped. This is disheartening to say the least, and in the long term it may be a very costly mistake. The problems started when the Internet bubble burst in 2000. Until then, DAC was growing to the point whereby few convention halls we... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 2

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

From Tool Agents To Flow Agents
By Brian Bailey - 30 Apr, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, in... » read more

Tape-Out Failures Are The Tip Of The Iceberg
By Brian Bailey - 24 Apr, 2025 - Comments: 5

The headline numbers for the new Wilson Research/Siemens functional verification survey are out, and it shows a dramatic decline in the number of designs that are functionally correct and manufacturable. In the past year, that has dropped from 24% to just 14%. Along with that, there is a dramatic increase in the number of designs that are behind schedule, increasing from 67% to 75%. Over the ne... » read more

Analog Creates Ripples in Digital Verification
By Brian Bailey - 24 Apr, 2025 - Comments: 0

We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.... » read more

AI Agents Need Goals
By Brian Bailey - 16 Apr, 2025 - Comments: 0

Experts At The Table: Definitions and goals matter when it comes to using AI effectively, and it has to be tightly reined in to be effective. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, including Johannes Stahl, senior director of product line management for the Systems Design Group at Synopsys; Michael Young, director of product marketing for ... » read more

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