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Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Analog’s Unfair Disadvantage


We live in an analog world, and yet digital has become the technology of choice. Mixed-signal solutions that used to contain significant amounts of analog, with just a small amount of digital signal processing, have migrated into systems where the analog to digital conversion happens at the very first opportunity. There are several reasons for this, and some of them build upon themselves. [g... » read more

Can Formal Replace Simulation?


A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

Researchers Learn New Tricks


There is very little EDA research being done in universities today, except for very narrow fields such as [getkc id="33" kc_name="formal verification"]. It has been a steady decline over quite a long period of time. There are several reasons for this. The first is money. Money has to flow into the universities to pay for the research, and this has to lead to some form of prestige for the est... » read more

Whatever Happened To High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verificati... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

The Hunt For A Low-Power PHY


Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

The Problem With Clocks


The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

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