A technology that improves overall verification efficiency by eliminating the repeated steps during compile and simulation.
The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve the verification productivity. Synopsys VCS Dynamic Test Loading (DTL) technology improves overall verification efficiency by eliminating the repeated steps during compile and simulation resulting in faster turnaround time (TAT).
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