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13-Gb/s Transmitter For Bunch Of Wires Chip-To-Chip Interface Standard

Unterminated and terminated impedance controlled drivers with feedback calibration enable transmitter power optimization.

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Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and unterminated driver topologies for different data rates and interconnect lengths. This paper presents a first ever reported transmitter implementation of this interface. Unterminated and terminated impedance controlled drivers with feedback calibration enable transmitter power optimization for a given interconnect based on the respective signal integrity at the receiver side. Results show that this transmitter can support both low and high speed low power communication between chips for interconnects up to 11mm length with energy consumption of 0.34pJ/bit at maximum data rate of 13Gb/s. The transmitter is designed and taped out in 22nm FDSOI technology node.

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