July 2009 - Semiconductor Engineering

Reflections Of A Cynic
By Ed Sperling - 31 Jul, 2009 - Comments: 0

Looking around the system-level design industry from the vantage point of DAC is like looking down on a bustling city from an airplane. It’s impossible to see all the different processes and technologies that go into creating a design from too high up, just as it’s almost impossible to see the entire system-level design from a single gate or memory subsystem or block. That’s the whol... » read more

How to Future-Proof A Hardware Designer
By Jon McDonald - 31 Jul, 2009 - Comments: 0

I’m at DAC this week, where there is a lot of interest and discussion on what’s going on in design and what’s going to happen to designers. One conversation with a university professor gave me a “eureka” moment. The professor had a student who really loved RTL design. The student asked him where he could get a job doing this, and the professor suggested the student move to India... » read more

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?
By Various Writers - 31 Jul, 2009 - Comments: 0

By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

Lots Of Work To Be Done
By Ed Sperling - 25 Jul, 2009 - Comments: 0

Many design engineers have had a long time to think about what’s changed in the design world. Some of them are still looking for jobs, frustrated by the remarkably slow pickup in the job market—particularly in the United States and Europe. But as Magma CEO Rajeev Madhavan noted last year, coming out of the downturn things may not look the same as when we went into the downturn. It’s ... » read more

DAC Attack
By Ed Sperling - 24 Jul, 2009 - Comments: 0

Designing chips has always attracted the best and the brightest minds. The sheer complexity of creating submicron technology creates challenges in mathematics, physics and science, and if intellectual stimulation ever wanes there’s always the problems associated with the next process node. Moore’s Law sees to it that new and interesting challenges always have to be met. But it does not... » read more

Experts At The Table: ESL And Low Power
By Ed Sperling - 24 Jul, 2009 - Comments: 0

Low-Power Design sat down with Walter Ng, senior director of platform alliances at Chartered Semiconductor; Brani Buric, executive vice president of sales and marketing at Virage Logic; John Sanguinetti, CTO at Forte Design Systems and Andrea Kroll vice president of marketing and business development at JEDA Technologies. What follows are excerpts of that discussion. LPD: As we go down the M... » read more

Pain Points In System-Level Design
By Ed Sperling - 24 Jul, 2009 - Comments: 0

Synopsys CEO Aart de Geus digs into what's changing in design, what's driving it, and what the future will bring. [youtube vid=a1ozKqlqVHs] » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy