August 2009

Experts At The Table: Building A Better Mousetrap

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

A Well-Engineered Leap Of Faith

The economics of engineering chips are changing again. We’ve been hearing for several process nodes about runaway non-recurring engineering costs and the rising costs of masks and how Moore’s Law would meet an abrupt end because no one could afford to stay the course. And while it’s true that not everyone did stay the course, the solution has turned out less onerous than many predi... » read more

Experts At The Table: Evolving Standards

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

What’s New And What Isn’t In ESL

By Jon McDonald Just because a problem can be solved doesn’t mean it has been solved. Last week I was on a panel at the ISLPED conference in San Francisco. This conference is focused on low power, and the panel addressed some of the things that are being done and some things needed for low power analysis exploration and trade-offs. While the panel was very interesting, one question that... » read more

System-Level Design Challenges

Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes. [youtube vid=HSgClJ9rQGk] » read more

End-User Report: Interoperability Still Lacking With System-Level Power Modeling

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

More Cores, Different Approaches

By Ed Sperling The general consensus among software developers is that some applications will never be able to take advantage of multiple cores, but that certainly doesn’t mean system designers can’t figure out ways to use more cores. Nor does it mean that all cores are created equal. The picture that is emerging from multiple chipmakers shows the following trends: More cores have lim... » read more

Hot Chips 2009: It’s All About Multicore And Low-Power

By Pallab Chatterjee The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities ... » read more

3D Integration: Extending Moore’s Law Into The Next Decade

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

Restrictive Design Rules, Take Two

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

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