May 2010 - Page 2 of 2 - Semiconductor Engineering

IP Integration Creates Challenges For Power

By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse. For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from m... » read more

Changes (For The Better) In Muticore Technology

By Ed Sperling - 13 May, 2010 - Comments: 0

By Pallab Chatterjee Subtle but important changes are occurring in the multicore world, particularly in the power per function that is available from each core. Two trends are increasingly evident. First, there is a growing need for higher-bandwidth data transfer or multiple-function processing for existing data transfer levels. And second, there is a shift to low power or mobile implement... » read more

A Shock To The System

By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

Making IP Tradeoffs For Power

By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs. Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to a... » read more

Experts At The Table: Verification Nightmares

By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: How important is a high-leve... » read more

Optimizing Physical IP For Applications And Processors

By Ann Mutschler - 13 May, 2010 - Comments: 0

What will the next challenges be for chip designers as the industry moves toward 28nm high-k metal gate manufacturing technology? One thing is for sure, power management may get even more painful without new innovations to handle the characteristics of 28nm. Optimization is definitely the approach that keeps creeping up as I talk with folks in the industry with ARM specifically mentioning ap... » read more

New Math: 1+1=1?

By Ed Sperling - 07 May, 2010 - Comments: 0

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

Money And Power

By Barry Pangrle - 07 May, 2010 - Comments: 0

By Barry Pangrle Companies developing products work within the realms of cost, features and quality. As the old saying goes, “choose two.” For chip design teams, the budget for the production cost of the chip is usually a constraint that is handed to them. Often that budget is not just the cost of the silicon but the cost for a finished part that is tested and packaged and ready to ... » read more