May 2010

The Great Divide

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

Balancing Quality, Cost And Locale

By Ann Steffora Mutschler As more features are packed into a single SoC there are simply more time-critical decisions to make. Instead of holding up one chip of a six-chip chipset, a delay or error on one chip can stop the whole parade. That explains why one of the most vibrant parts of the business at big EDA companies these days is standard IP, and why most of the other commercial IP make... » read more

Unified Design Flows Require New Skill Sets

By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more

The Unifying Promise Of 3D

There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump. Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chi... » read more

Constraints Management

As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the t... » read more

How Good Is Good Enough?

By Jon McDonald I’ve heard a few comments recently questioning how good is good enough. How good does a device have to be before it’s above questioning its capabilities? When designing some new whiz-bang device how do we know when we can stop? I think most engineers will agree there is always room for improvement. There are additional optimizations, refinements or alternative approaches... » read more

Why So Formal?

By Bhanu Kapoor Let’s take a look at the types of power management verification issues that are most suited for formal verification and how formal techniques complement dynamic simulation-based verification in some of the challenging tasks associated with validating SoC power management architectures. There are three main categories of formal tools in use today: Equivalence Checkers, Asse... » read more

Same Industry, Different Shape

As the design industry plunges into DAC this year, it’s beginning to look like a completely different industry. It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of... » read more

It’s The Architecture

Power optimization is a system issue. How many times have you experienced your cell phone provider sending your phone an update and the battery lifetime then improving? The hardware team built in the hooks but there just wasn't enough time to get the software together and tested before the product needed to ship, so the improved functionality shipped later. Well, that's at least one advanta... » read more

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