The Unifying Promise Of 3D

IC stacking could bridge the gap between those following Moore’s Law and those falling further and further behind.


There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump.

Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chips that used to be in a package is a lot different than designing a chip where the logic may be spread across two or more die that are bonded together. And putting memory on top of a processor and calling a 3D chip is not the same as optimizing the chip for performance, power and understanding the thermal implications of putting one block on top of another.

On the flip side, everyone is talking about the same direction. It’s just a question of where they sit on that evolution from system-in-package to a true 3D layout and synthesis. Memory makers are already building 3D configurations, and some of the most advanced chipmakers are already working on 3D chips they’re not willing to talk about just yet.

The next step is to commercialize this process beyond just a few, which is where EDA tools come in. The companies that can bridge the gap between the most advanced digital processes and lagging analog processes stand to profit handsomely because they will be acting as a bridge between the economic necessity of some companies to push forward to the next node and the economic pain that kind of approach is causing other companies.

There is much work to be done in this area, of course. Modeling in 3D doesn’t exist today. Through-silicon vias are still a work in progress. Secondary problems such as electrostatic discharge, electromigration and parasitics need to be dealt with. Thermal issues need to be dealt with at the architectural stage. And standards have to be developed across the board.

But none of these is new. What is new is the prospect of unifying both ends of the semiconductor spectrum in SoCs that can both improve performance and use less power, which can use the manufacturing process that makes sense for a particular technology, and which can re-use vast amounts of previous chips to lower the overall cost of development.

In semiconductor design, 3D stacking is an enormous opportunity. The only question now is who will get there first.

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