November 2010

Standards Update

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

Reducing Bottlenecks

By Ann Steffora Mutschler For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery. While it has caused concern, it is important to note that the Tianhe-1A use... » read more

Building Up In 3D

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

Changes Ahead

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process. To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes ... » read more

Just Kidding

By Jack Harding I can remember back to 1995 and the first time I heard Joe Costello at Cadence speak publicly about the “disaggregation of the supply chain.” Disaggregation? Was that even a word in Webster’s Dictionary? It didn’t matter because, like many other concepts championed by Joe, it was the word every journalist and analyst in the semiconductor space was using to describe t... » read more

Behind The Standards

By Kurt Shuler As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there's much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transacti... » read more

Getting Some Respect

He’s a comic legend. The master of the one-liner. I had the good fortune of being in a comedy club in New York City one evening a long time ago when Rodney stopped by to try out a new comedy routine. He simply walked in and took the microphone for 45 minutes. Apparently, he did those impromptu appearances a lot “back in the day”. One of Rodney’s most famous one-liners is “I don't get ... » read more

Out Of Context

By Jon McDonald A rose by any other name is still a rose. I have had the opportunity to speak with a number of different groups recently, covering everyone from systems engineers focused on specifications and documentation to software teams, architects and implementation groups. Each group has their own unique language, their own unique way of communication. Some of the most entertaining co... » read more

ARM Vs. Intel

Simon Segars, ARM's executive vice president and general manager of the company's physical IP group, talks about the war with Intel and which markets it's likely to affect. [youtube vid=EISi5qpY77M] » read more

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