Standards Update

What’s changing in system-level modeling for TLM 2.0, OCP and Open Modeling TAB.


By Ann Steffora Mutschler
In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign.

The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB at Si2.

For TLM-2.0, OSCI president Mike Meredith said work currently is focused on moving the TLM-2.0 APIs into the SystemC language under IEEE 1666 2010 to be included in the SystemC Language Reference Manual (LRM).

In the midst of that work, Meredith noted there is also work being done to improve the way things are described, and to eliminate some ambiguities in TLM-2.0.

One of the biggest clarifications being made is better formalization of the TLM-1.0 and message-passing interface. While the TLM-1.0 standard was released some time ago, part of it is incorporated in the TLM-2.0 standard as legacy; the TLM-2.0 standard doesn’t precisely build on top of those APIs but TLM-1.0 is being clarified as part of the integration, he explained.

“The old OSCI TLM-2.0 standard document describes the TLM-1.0 API but doesn’t formally describe it in as rigorous a way as an IEEE language reference manual does. So the goal of an IEEE manual and standard is that someone implementing it should be able to do so just looking at the standards document. It wasn’t really that clear in the OSCI document, so that’s been formalized,” Meredith continued.

Next, due to the fact that IEEE 1666 is the core language (and is not just TLM), there is core language being updated. Since there is already a good and rigorous standard for the current SystemC definition, some additional capabilities are being added to make it easier to model the software process, among other things, he said.

Among the additions to SystemC are process control extensions, which include a set of APIs for allowing better control of dynamic processes. There is already a mechanism for spawning processes and systems dynamically. This adds APIs and semantics for suspending those and restarting them, for example, and for one process killing another process.

These additions will make it easier to write models and create the simulation. Once a simulation is started in the current version of SystemC, if stopped it cannot be restarted. These are helpful for allowing modeling and for allowing instrumentation, and either customer tooling or EDA vendor trolling to have an opportunity to get out the state of the simulation at some particular point and report it to the user.

Related to the updates in TLM are activities in OSCI’s configuration, control and inspection (CCI) and Analog/Mixed-Signal (AMS) working groups.

The CCI working group is developing a set of standards and APIs for use with transaction-level models. “While TLM is defined to provide interoperability for communication of memory mapped SoCs, what the CCI APIs are designed for is to provide a standard way for testbenches, semiconductor user tooling or EDA vendor toolsets to configure models,” Meredith noted. The configuration APIs are currently in development.

Also under OSCI, while it might seem odd at the outset, there is also work underway to develop an analog/mixed-signal extension to TLM-2.0. AMS is a current OSCI standard in use that was built to allow system-level models to have some analog computations to represent the mixed signal part of the SoC and the real world.

“For SoCs that contain sensors or actuators, it may be easier and more accurate to use analog techniques for modeling what’s happening at that sensor—up to the part where you get to the digital circuitry—than it is to try to write a software model that digitally pretends to be the real world. This allows a mixture of transaction-level system models with bits of AMS computation usually around the edges,” he added.

Jumpstarting ESL design
In the Open Core Protocol International Partnership (OCP-IP), the organization recently completed collaboration with India-based SystemC modeling and embedded software developers CircuitSutra, along with U.K.-based software virtual platform infrastructure provider Imperas, that resulted in a Virtual Platform Demo. The VPD was created with OCP-IP’s Modeling Kit and is meant to act as a guide to OCP-IP members to allow them to quickly start ESL activities using the OCP-IP TLM Modeling Kit, which is fully compatible with OSCI’s TLM 2.0.1.

The Virtual Platform Demo leverages Imperas’ Open Virtual Platforms (OVP) technology, which was created to make virtual platforms more accessible and easier to use for embedded software development. It includes the OVPsim simulator, model libraries including nearly 50 different processor core models, and modeling APIs that allow users to easily create their own processor, peripheral and platform models. OVP processor models include a SystemC/TLM-2.0 interface for integration in those virtual platform environments.

CircuitSutra built a comprehensive virtual platform that boots the busybox embedded Linux operating system in about 10 seconds, and can be used for embedded software development. Features like run-time bindability and memory management provided in the OCP Modeling Kit are used in the platform.

Peripheral models support TL4 and TL3 abstraction levels, and models can be further refined for lower abstraction levels (TL2, TL1). They are supported by other powerful features of the OCP-IP TLM Kit such as timing information distribution, non-default timing, OCP specific payload extensions and phases, etc.

The example platform makes heavy use of the OCP-IP Modeling Kit which was developed by OCP-IP member companies working in collaboration with Greensocs, Ltd. It interoperates seamlessly with other TLM utilities, such as GreenSocket from GreenSocs and the methodology used is equally applicable to other buses and platforms, providing, and proving a TLM-2.0 based commonality of approach.

OCP’s System Level Design Working Group Architect, James Aldis, an SoC architect from Texas Instruments, explained that the group has been working to try to extend the definition of the OC protocol to cover not only RTL interface but also the interfaces used when building virtual platforms and verification models and architectural exploration models of an SoC. “To that end we’ve defined APIs at different levels of abstraction in SystemC into the technology we are currently using is derived from the OSCI TLM-2.0 base protocol.”

As well as defining the API, the OCP’s SDL working group provides a significant amount of code which helps people to write and create models which are compliant with OCP’s APIs to enable reuse of models as well as reuse of RTL and so on for SOC components, he said.

“People can now download from the OCP-IP a virtual platform or the source code for a virtual platform which uses the OCP IP system level design technology and enables them to see how such things can be built and how they stick together,” Aldis explained. “It demonstrates the value of the code but at the same time it’s actually a useful thing in itself. It’s a simple ARM9-based unit running a limited operating system and you can get this working with a pretty low effort. If you know a little bit of a SystemC and TLM, then you can start adding components to it, modifying the components that are there, and play with the architecture of the modeled system-on-a-chip.”

While there are other ways to do this, OCP-IP wanted to demonstrate how to use a public standard TLM reuse interface and a virtual platform. The group does plan to update the platform and demonstrate some of the more challenging features of a bus interface to model including semaphore support, but not likely until the second half of 2011.

Pointing back to power
Everything comes back to power these days. Even with system-level modeling standards, the power issue comes front and center right away.

While standards body Si2 did begin an Open Modeling Coalition (OMC) about five years ago based on demand from multibillion-dollar IDMs to do more accurate, flexible and efficient modeling, president and CEO Steve Schultz explained it was despite trepidation on behalf of the Si2. “When Si2 was asked to get into this, we were hesitant because in the past there had been an effort at Si2 for six or seven years and it was all around the DCL (delay calculation language).”

Fast forward to today. Si2 maintains its Open Modeling Technical Advisory Board (OMTAB), which succeeded the Open Modeling Coalition (OMC) with technical objectives to define a consistent modeling and characterization environment in support of library representations for improved integration and adoption of advanced library features and capabilities, such as statistical timing, characterization information, and an Open Modeling Calculation Interface (OMCI).

The OMTAB will support delay, power, and noise modeling for library cells, macro-blocks and IP blocks, and provide increased accuracy to silicon for sub-65nm technologies, while being extensible to future technology nodes, according to Si2’s website. Technology contributions from several companies are in support of these goals, and the group is open to new member.

Today, Si2’s work in the low-power space overshadows all of its efforts given the intense need in the industry for power-aware everything.

“The biggest opportunities in power savings are at the higher levels of abstraction but it is harder to do a model at that level,” Schultz said. “And frankly, whether it’s the semiconductor industry or the EDA industry, they have not figured out what you need to model for power at those different abstraction levels and how you present that information to a tool. How much work you need to go through at how many levels? We are at the point now on the semiconductor industry road map, if you look at the ITRS just three to five years out, where power is becoming one of the major limiting factors in the continued health and revenue of our semiconductor industry. They can’t continue the integration because of these power issues. As such it is absolutely critical that we do a better job on power then just doing clock gating. It’s imperative.”

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