May 2012

Tech Talk: Power Issues Ahead

Aveek Sarkar, vice president of technology and support at ANSYS Apache, talks with Low-Power Engineering about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models. [youtube vid=-7TtszsuZP0] » read more

Executive Briefing: Trillion-Gate Designs

Wally Rhines, CEO of Mentor Graphics, talks with System-Level Design about what's needed for trillion-gate designs, the increasing demands of verification and emulation, new tools for stacked die and the trend toward designing for the enterprise. [youtube vid=pQs1qNkFvVo] » read more

Executive Briefing: Orchestrating Change In IC Design

Cadence CEO Lip-Bu Tan sounds off to System-Level Design about what's changing in EDA, in Cadence, in the supply chain, and the need to make it all work together. [youtube vid=iwl5HOs4UsU] » read more

Executive Briefing: Making Derivative ICs Better

Naveed Sherwani, CEO of Open-Silicon, talks with System-Level Design about pain points in design, hardware-software co-design, derivative chips, what's missing in tools flows and the need for a deeper understanding of IP. [youtube vid=5BGck8Fm5Fo] » read more

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  ~~ The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations ... » read more

Experts At The Table: IP Subsystems

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that co... » read more

Getting Ready For 20nm

By Ed Sperling and Mark Lapedus Despite hurdles in getting 28nm rolling and predictions that process technology will stick around for years to come, there appears to be rapidly growing interest in 20nm—at least from the design side. This is significant for a couple reasons. First, for most companies 20nm will be the first encounter with double patterning because EUV still is not viable—... » read more

Options And Hurdles Come Into Focus For 3D Stacking

By Mark LaPedus The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market. There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs. The enormous risk to bring ... » read more

The Hidden Costs Of Directed Self-Assembly

By Mark LaPedus Directed self-assembly (DSA) has been billed by some as a potential paradigm shift in semiconductor manufacturing, but it may not turn out to be quite the panacea its proponents suggest—or at least not yet. There are many questions surrounding DSA, an alternative lithography technology that makes use of block copolymers to enable fine pitches. Key among those questions ar... » read more

ASMC: TSVs Needed as Scaling Challenges Mount

By David Lammers With the industry facing challenges in the introduction of EUV lithography and high costs for double patterning, TSV introductions have taken on heightened importance, participants said at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held in Saratoga Springs, N.Y. in mid-May. Risto Puhakka, president of market research firm VLSI Research Inc., said the g... » read more

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