Getting Ready For 20nm

By all accounts this node is going to be expensive and problematic, but there is no shortage of interest or investments by chipmakers and foundries.


By Ed Sperling and Mark Lapedus
Despite hurdles in getting 28nm rolling and predictions that process technology will stick around for years to come, there appears to be rapidly growing interest in 20nm—at least from the design side.

This is significant for a couple reasons. First, for most companies 20nm will be the first encounter with double patterning because EUV still is not viable—and there is no clear timetable when it will be. And second, it’s just one process node away from where companies are expected to begin triple or quadruple patterning and using FinFETs to replace planar transistors. Rather than risk multiple changes at once, companies appear to be hedging their bets and dealing with one problem at a time.

“There’s a lot of anxiety about double patterning,” said Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-to-Silicon Division. “There’s basically one license required for double patterning and we already have 20 paying customers. This is the first such blatant signal that companies are moving in this direction. It’s as aggressive a push as we saw at 28nm, plus a couple of new companies.”

Double patterning has its share of challenges for design teams. The pitch on each side is supposed to be divided in half, but deciding where to actually create the split in a design isn’t easy. Sawicki said it makes optical proximity correction far more complex—and more expensive. It takes almost twice as many processors to run the large file sizes for double patterning. And that’s just on the design side. On the manufacturing side, the shift from dummy fill to smart fill reduces the process variation, but add in process variation and an increasing number of corners and it gets still harder—and, once again, more expensive.

Follow the money
In April, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) raised its capital spending to the $8 billion-to-$8.5 billion range for this year. The new CapEx plan is a strong upward revision from the earlier plan to spend $6 billion for this year on capacity expansions.

As part of the plan, TSMC accelerated and pulled in the construction of a 20nm R&D process line. In terms of capital expenditures, TSMC will spend $1.3 billion to $1.5 billion on 28nm capacity expansions, $700 million on 20nm, $200 million on image sensor and embedded flash, and $100 million on its new turnkey 2.5D/3D chip stacking line.

“28nm is turning out to be a roaring success,” said Morris Chang, chairman and chief executive of TSMC, during a recent conference call. “In 20nm, the ramp up will be faster than 28nm.”

Therefore, at 20nm, Chang encouraged customers to engage with TSMC much earlier than previous process generations. TSMC’s move to accelerate its 20nm pilot line will allow the company to “shorten the learning cycle” for customers, Chang said.

TSMC has been ramping up 28nm for some time, with plans to move to early or “risk production” for the 20nm node by the end of 2012. The definitions of “risk” and “pilot” production vary from company-to-company and it’s unclear which foundry vendor is actually ahead at 20nm.

At 20nm, GlobalFoundries plans to move into risk production in the second half of this year, followed by volume production next year. “We have a very competitive 20nm offering following right on the heels of 32/28nm,” said Michael Noonen, senior vice president of worldwide sales and marketing at GlobalFoundries.

“It has been well endorsed by the marketplace because it is the most comprehensive, cost-effective platform in the industry,” he said. “Technology development is moving full-steam ahead and our Fab 8 in New York began running full-loop 20nm silicon in January. We have multiple active customer design activities with silicon delivery expected by 2H 2012.”

Samsung Electronics Co. plans to have 20nm qualified and ready for production in the second half of 2012. Rival United Microelectronics Corp. (UMC) will move into 20nm “pilot production” by mid-2013.

UMC recently broke ground for its 300mm Fab 12A Phase 5 and 6 complex, located in Tainan, Taiwan. Phase 5 and 6 will provide 28nm, 20nm, and 14nm capacity. The fab is scheduled to move in equipment during the second half of 2013.

In a statement, Stan Hung, chairman of UMC, said, “Cumulative CapEx for UMC’s Fab 12A phases 1-4 is projected to reach $8 billion, with P5 and P6 to add nearly $8 billion more. There are further plans for P7 and P8.”

In total, phase 5 and 6 has a cleanroom area of 53,000m2, about the size of 10 American football fields. The phases are expected to contribute 50,000 wafers per month, bringing total monthly design capacity for Fab 12A to 130,000 wafers. With the planned Phase 7 and 8, the eight phase fab complex will have a total design capacity of 180,000 wafers per month.

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