The Hidden Costs Of Directed Self-Assembly

Alternative litho methods are under study at universities, but real commercialization is unlikely before 10nm.

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By Mark LaPedus
Directed self-assembly (DSA) has been billed by some as a potential paradigm shift in semiconductor manufacturing, but it may not turn out to be quite the panacea its proponents suggest—or at least not yet.

There are many questions surrounding DSA, an alternative lithography technology that makes use of block copolymers to enable fine pitches. Key among those questions are when will DSA move into semiconductor production, what are the challenges for the technology, and what it will actually cost.

In theory, a university or research center could set up a DSA line for R&D for a mere $2,000, said Christopher Bencher, a member of the technical staff at Applied Materials, at a recent event. It’s unlikely that a university will produce complex multicore processors using DSA, but for years researchers have been conducting R&D and developed devices with DSA for a small cost.

It’s a different story to bring DSA from the lab to the fab, however. To insert DSA into production, a chipmaker would still need to own a leading-edge fab and 193nm immersion scanners, said Moshe Preil, manager of emerging lithography and tools at GlobalFoundries.

A new, leading-edge fab is projected to cost from $4.85 billion to $6.7 billion. But generally, a chipmaker could utilize an existing leading-edge fab and tools, and make relatively few new equipment purchases, to put DSA into production, Preil said. “I don’t think the cost to put DSA in production is going to be that outrageous,” he said.

The most obvious cost savings is lithography. With DSA, chipmakers could use existing 193nm tools—and push out the need for extreme ultraviolet (EUV) lithography. A 193nm immersion tool runs about $40 million. In contrast, a EUV scanner is projected to sell for $125 million per unit.

There are bigger hurdles to bring DSA into chip production. Current block copolymers based on today’s poly (MMA-co-styrene) materials could run out of steam at 11nm. There are still defect issues with DSA. And arguably the biggest hurdle is to develop a new design methodology around DSA.

Litho roadmap
For some time, leading-edge chipmakers have been evaluating several lithographic options for 14nm. There is a glimmer of hope that EUV will be ready at 14nm, but there are signs the technology is running into more delays due to inadequate power sources.

If EUV is late, the only option is to use 193nm immersion and a multi-patterning scheme at 14nm. Then, at 10nm, the IC industry is looking at several options: DSA, EUV, maskless, multi-patterning and nano-imprint.

Some believe that DSA could get inserted as early as the 14nm node. GlobalFoundries’ Preil said that a more realistic insertion point for DSA is 10nm. “It’s really too late to insert DSA at 14nm,” he said. “Progress continues to be made at the sort of rate that we need it for the 10nm node.”

Technically, DSA is not a next-generation lithography (NGL) tool. It’s a complementary and double-patterning scheme. DSA enables frequency multiplication through the use of block copolymers. When used in conjunction with a pre-pattern that directs the orientation for patterning, DSA can reduce the pitch of the final printed structure.

Using 193nm immersion, DSA has demonstrated the ability to print images down to 12.5nm—without the need for multi-patterning. DSA could extend 193nm lithography beyond 10nm, eliminate expensive multi-patterning steps and push out EUV. On some roadmaps, there is a path to use EUV and DSA simultaneously to scale devices beyond 14nm.

There are two types of DSA methods: graphoepitaxy and chemical epitaxy. In chemical epitaxy, self-assembly is guided by chemical patterns. In graphoepitaxy, self-assembly is guided by pre-patterned templates.

Stanford University has been developing a DSA design methodology using individual guiding templates. Using 66nm templates, Stanford has demonstrated 25nm contact holes for 22nm SRAM cells. The end goal is to develop a “full character alphabet set of templates,” said H.S. Phillip Wong, professor of electrical engineering at Stanford University. “The templates would allow designers to compose any arbitrary feature.”

Even so, there are design challenges. Regarding the DSA templates, “the list of what you can do is still very limited,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. “You would also be tied to very restrictive design rules or proscribed design rules.”

Design-for-manufacturing techniques like pattern matching aren’t exactly straightforward in DSA. With DSA, a design-rule-checker (DRC) may have to implement a “reverse pattern matching” technique, Abercrombie said.

DSA’s cost of ownership
Today, the DSA process flow is ahead of the design infrastructure. AZ Electronic, IBM and the University of Wisconsin have separately developed process flows, each aimed at moving DSA from the lab to the fab.

Unlike today’s chip production, which is dependent on lithography, DSA revolves around conventional wafer track systems, etchers and inspection gear. “For basic DSA, you need a coater and a bake plate, plus a way of generating the guide structures. Since the guides need to be fairly small, you need at least 193nm dry lithography, or for a university, more likely an e-beam tool” to pattern the individual guides, said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications.

“Then, you need to etch or at least decorate the structures, and a scanning electron microscope (SEM) or an atomic force microscope (AFM) to observe them. Wet development is also possible, at least for contact holes. ,” Dammel said. “For our customers, they already have all of the needed tools in-house. So, for R&D, no new equipment is needed. For production, it becomes a matter of track capacity. But, of course, the cost of track equipment is far cheaper than that of an EUV tool.”

The cost of ownership depends on several factors. “Assuming a university has standard tooling, their cost would be near zero,” he said. “For thermal annealing, a university could cobble something together for a few dollars.”

On the other hand, a chipmaker would still need to invest in new and more advanced materials, such as higher k films and metal gates, said GlobalFoundries’ Preil. The cost of the DSA materials themselves are expected to be similar to today’s photoresists, he added.

Another challenge is how to scale the DSA materials. AZ Electronic, Dow, JSR, SEH, TOK and others are developing next-generation DSA materials. Recently, CEA-Leti, Arkema and the Laboratoire de Chimie des Polymères Organiques devised a DSA development platform that enables a 20nm pitch and contacts down to 7nm.

Block copolymers consist of different polymer chains that are joined. Copolymers can be separated into ordered nanostructures. The inherit properties enable them to frequency double or quadruple into regular patterns. And a range of phase morphologies can be accessed depending on the block lengths.

“For 10 nm, p(MMA-co-styrene) block copolymer is no longer a suitable material. Its low chi factor implies that a high molecular weight (MW) is needed to obtain phase separation,” AZ’s Dammel said. “Since MW is related to domain size, the lowest line-space structures that can reliably be made are approximately 11nm.”

The goal is to develop higher chi materials for 10nm node and below. The University of Queensland in Australia is developing a promising class of diblock copolymers called PS-b-PDLA. Though in the R&D stage, these materials will make it “possible to extend DSA to the 8nm node, using guide structures made by immersion lithography,” he said.