May 2012 - Page 5 of 6 - Semiconductor Engineering

The Next Steps
By Aveek Sarkar - 10 May, 2012 - Comments: 0

By Aveek Sarkar Remaining competitive in today’s semiconductor market means IC designers must meet performance, power and price targets for their design, regardless of the end application. Meeting these mutually conflicting goals requires enlisting the use of several architectural and design techniques, including three-dimensional (3D) or stacked-die architectures that can help meet perfo... » read more

ESL Power Models
By Ed Sperling - 10 May, 2012 - Comments: 0

Low-Power Engineering discusses what's missing from the ESL tool chain with Ghislain Kaiser, CEO of Docea Power. [youtube vid=hV5viEgLIvA] » read more

LP Macros
By Luke Lang - 10 May, 2012 - Comments: 0

By Luke Lang Many designers have asked why CPF has the macro model commands while UPF/1801 does not. I will try to answer this question and explain the differences in both approaches. First, let’s briefly review CPF macro model. A CPF macro model describes the power interface of a macro cell, which could be a complex cell (pad cell), an IP block (memory), or a hardened block (ARM core). F... » read more

Intel’s Hot New Tri-Gate Processors
By Barry Pangrle - 10 May, 2012 - Comments: 0

By Barry Pangrle Intel announced its newest third-generation Core processors on April 23rd. There has been much anticipation surrounding these new chips from Intel, largely because of their new 22nm tri-gate process technology used to fabricate these devices. Figure 1, from the presentation entitled, “Intel’s Revolutionary 22nm Transistor Technology,” by Mark Bohr and Kaizad Mistry, s... » read more

Little Shifts, Big Changes
By Ed Sperling - 10 May, 2012 - Comments: 0

Every decade or so changes come along in IC design that look evolutionary, but which pack a wallop of side effects—some good, some bad, some challenging. But the next few process nodes, while evolutionary in many respects, changes will drive us deep into the realm of physics and mathematics. Research is already well under way in these areas. TunnelFETs use electrons to literally tunnel thr... » read more

Standards: Too Many or Not Enough?
By Kiran Vittal - 10 May, 2012 - Comments: 0

Many of you are familiar with the Betamax versus VHS format wars in the late 1980s. If you’re not old enough to remember that one, you’ll remember HD DVD versus Blu-ray. In each of these cases, there was a clear winner. Semiconductor design has these format wars, too. The problem is that there is rarely a clear winner and worse, sometimes we miss the standard altogether. There are tw... » read more

The Bigger Problem
By Bhanu Kapoor - 10 May, 2012 - Comments: 0

By Bhanu Kapoor Getting power management features already built into chips to be fully utilized is indeed the bigger problem. The features here refer to hooks provided by power management techniques such as voltage and frequency scaling, power gating, and threshold voltage scaling. There is no doubt that these features have helped a lot in optimizing power consumption. But they are mainly a... » read more

Power Becomes Bigger Issue In Stacked Die
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

Mixed-Signal Integration Drives Platform Chips
By Ann Mutschler - 10 May, 2012 - Comments: 0

Not only are there low-power challenges with just about every design today, there are also very interesting issues concerning integration of mixed-signal onto chips. As chips are get bigger and more costly to develop, many companies are turning to platform chips that can be used in a smartphone and in a tablet with slightly different twists in the functionality of that platform chip because ... » read more

Photomask Market to Hit $3.35 billion in 2013
By Lara Chamness - 09 May, 2012 - Comments: 0

by Lara Chamness, senior market analyst, SEMI Industry Research and Statistics The worldwide semiconductor photomask market was $3.12 billion in 2011 and is forecasted to reach $3.35 billion in 2013. After reaching a market peak in 2010, the photomask market grew another 3 percent in 2011 to set another market high. The mask market is expected to grow 4 percent and 3 percent sequentially ove... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy