November 2012 - Page 4 of 5 - Semiconductor Engineering


The Growing Integration Challenge


By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

Power Impacts On Advanced Node IP


By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

New Incentives For Lowering Power


By Ed Sperling Despite all the focus by design teams on lowering power over the past few years, in many applications power is still the last consideration for many companies in the power-performance-area equation. That’s beginning to change, however, even for applications that in the past have not been particularly power-sensitive. There are several reasons for this shift. No. 1 on the li... » read more

Automated Assembly And IP Integration Techniques For SoCs


Over the past few years, the consumer revolution has generated a significant growth of system-on-a-chip (SoC) designs mainly in the area of consumer electronics. The consumer revolution has led to a trend in convergence of applications on a single device. The biggest such example is the Smartphone or Tablet – handheld devices such as the iPhone or the iPad. These devices can enable consumers ... » read more

Signal Integrity’s Growing Complexity


By Matt Elmore In Part 1, we reviewed the importance of simultaneous switching output (SSO) timing and the challenges associated with double data rate (DDR) simulation complexity. DDR memory interfacing has reached incredible levels of performance (17 Gb/s), requiring precise quantification and reduction of noise. In order to account for each noise contributor, we must model systems end-to-... » read more

Technologies For Power, Signal, Thermal And EMI Sign-off


This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines. To download this white paper, click here. » read more

CPF 2.0 Voltage Regulator And Analog Ports


By Luke Lang CPF 2.0 was released more than a year and half ago, yet the majority of the designs are still done with CPF 1.1. This is one of those good news/bad news situations. The good news is that CPF 1.1 is perfectly adequate for majority of the LP designs. The bad news is that designers may not be aware of the new CPF 2.0 features that could be quite useful. This month, we will take a loo... » read more

ARM’s big.LITTLE Concept


By Barry Pangrle ARM EVP Simon Segars gave the opening keynote address at last week’s ARM TechCon in Santa Clara, California. The big announcement was the new ARM Cortex-A53 and Cortex-A57 processors that will operate in ARM’s “big.LITTLE” configuration. I wrote a bit about big.LITTLE in my blog last year on Innovation at the Core. ARM’s big.LITTLE concept is based on using a smal... » read more

Roundtable: Lower-Power Chips


Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

iPad Mini: The iPad On A diet


By Cary Chin The iPad mini was unveiled last month, but just hit the stores on Nov. 2. Early reviews have been quite positive—good performance, quality build, excellent battery life. There’s just one problem (besides the price)—the non-retina display. Even with a 1024 x 768 display (the same resolution as the original iPad and iPad 2), it seems we’ve gone “retina display” mad, and ... » read more

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