May 2013 - Page 4 of 6 - Semiconductor Engineering

President Obama Visits Applied Materials
By Applied Materials Writers - 16 May, 2013 - Comments: 0

By John Kania [caption id="attachment_8398" align="alignnone" width="518" caption="Applied Materials CEO Mike Splinter with President Barack Obama as they tour the Austin manufacturing clean room and hear from Applied employee Nilam D. Bhakta-Sahib about the complex chip making process. "][/caption] President Obama rode Air Force One into Austin, Texas, to shine a spotlight on the import... » read more

EUV Flare And Proximity Modeling And Model-Based Correction
By Various Writers - 16 May, 2013 - Comments: 0

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in seve... » read more

Moving Targets
By Ed Sperling - 16 May, 2013 - Comments: 0

There is a very close correlation between power and complexity in an SoC. The more functionality that is required to meet market demands, the greater the need to push to the next process node in order to fit it all onto a single die. The result is more power density, and more attempts to limit the effects of that density with power islands, different voltages, gating, and a variety of other tec... » read more

Bigger Wafers, Bigger Risk
By Ed Sperling - 16 May, 2013 - Comments: 0

At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

FinFET Isolation: Bulk vs. SOI
By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

FinFETs On SOI
By Ed Sperling - 13 May, 2013 - Comments: 0

Soitec's Steve Longoria talks with Semiconductor Manufacturing and Design about what's changing at the leading edge of Moore's Law and why those changes are necessary. [youtube vid=K6D39QqJWSU] » read more

Cost vs. Value
By Ann Mutschler - 10 May, 2013 - Comments: 0

By Ann Steffora Mutschler The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together. “... » read more

Power Becomes Bigger Issue In Stacked Die
By Ed Sperling - 10 May, 2013 - Comments: 0

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Executive Briefing: Andrew Yang
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

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