Executive Briefing: Andrew Yang

Apache’s president talks about how power has moved from important to critical at leading-edge process nodes, and what will be needed to continue Moore’s Law.

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By Ed Sperling
Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation.

LPHP: What’s the most important issue these days for chipmakers?
Yang: According to the feedback we’ve gotten from our customers, power is the key. It’s now really important. In the past they told us that power was growing in importance, but this year they say it’s critical.

LPHP: At what process node?
Yang: The leading one is 20nm. They are taping out at 16nm using that process. And for that process node, power clearly is the key. All of this is application-specific, of course. If it’s going into a mobile device, that’s even more important. But even if it isn’t going into a mobile device, power is still a key metric. It’s power budgeting, power reduction, how much power consumption can you predict? And preferably you should do this as early as possible—at the RTL stage—so action can be taken. Visibility is there at that point to still guide the design. That’s one key front they’re wrestling with. The second challenge is on the signoff front involving the power delivery network. That includes reliability and noise induced from the power source.

LPHP: There are lots of disconnected pieces in power, which makes signoff difficult, right?
Yang: When you have signoff, you have a certain level of confidence in the design. We have signoff in verification, timing, cross-talk and yield analysis. We also have signoff for the power delivery network, which is the implementation. We aren’t even close to signoff for power consumption. That’s more like power estimation, and for that we want to do predictions about the consumption of power as early as possible—preferably even at the architectural level. But you also want it to be accurate, and if you do it early you don’t have the physical design to base that on. You don’t have technology information and load-in conditions. Absent of those, how can you do a good job in accurate estimation? You need help from previous designs and test chips, or any data that can give you insights. From that, you can predict the power consumption.

LPHP: How does that affect reliability?
Yang: We need to distinguish between reliability and signoff of the power delivery network—the wire size, the interconnect, how many layers, what kind of via structures, bump placement, package—all of which will affect the signoff. Reliability is actually something more concrete. It’s a real number, so you can try to meet the target. It falls into the traditional realm of signoff. The foundry sets the target and the design team runs the design, analyzes it and matches it against the target. If they meet the target, they can sign off. Reliability is a key signoff criteria. Static IR drop also has a metric number, and it’s also part of signoff. The challenge is transient or dynamic voltage drop and ground bounce. Those are more difficult because they relate to issues such as design coverage, logic switching, timing property—all of those things have an important impact on dynamic voltage drop and ground bounce. We can have signoff for reliability, but for dynamic voltage drop, ground bounce including package effects are important things we need to work together to solve. And without signoff for those areas, chips will always be subject to uncertainty.

LPHP: Doesn’t this cross boundaries between EDA and manufacturing?
Yang: Yes. In the past, chips were designed independent of the package and vice versa. A power delivery network is not constrained within the chip. It propagates through the bump to the package and the board. So when we talk about signoff for power delivery, the package effect is very important.

LPHP: When chipmakers design chips, do they usually consider the package for power-related issues?
Yang: Often the package is considered early on, and it’s governed by the cost. The marketing guys decide the type of package based on pricing, so the designer has to enforce this. That adds more challenges to the design process, which is why we have chip-package co-design—that’s becoming an important part of power signoff.

LPHP: What happens when we move into 2.5D and 3D stacked die?
Yang: One of the biggest motivations of going to 2.5D and 3D is power. A lot of power is consumed in the I/O switching. But 2.5D and 3D shortens the I/O channels and increases the bandwidth for chip-to-chip communication. If data has to travel a longer distance it requires high-power consuming I/O buffers, so if you can stack the die it shortens the distance. You can use simple buffers instead of sophisticated I/O devices.

LPHP: Are any production stacked die chips out?
Yang: Only from the FPGA vendors. The benefits are compelling, though, and a lot of people are looking at it. Right now it’s waiting for a big success story. Then the industry will move in that direction. But to do that, the manufacturing and the tools have to be ready.

LPHP: Will companies choose one path over another—finFETs vs. stacked die?
Yang: Cost is going to be the driving factor. The cost of doing 14nm and 10nm are getting so high that maybe only a few companies will be able to play there, and the rest will be slowly adopting the next process nodes while trying to leverage mature process nodes. They will focus more on traditional applications and add in more components to make smarter mixed signal and smarter analog designs. So there is a dichotomy in the market.

LPHP: Are you seeing any slowdown on the leading edge?
Yang: No, there is no slowdown in Moore’s Law.

LPHP: So where do you put most of your effort?
Yang: Our business has been driven by the top 20 semiconductor companies, so clearly we gravitate toward these customers. They care a lot about power. They are following Moore’s Law. They care about signoff. And so we are serving those customers and supporting them. We still believe the rest will catch up at some point, and for them power will be very important.

LPHP: So what you develop on the leading edge can be used at older nodes?
Yang: Yes. The same techniques, capacity and accuracy will benefit everyone. For the majority, they are doing some soul searching to find their own niches where they can differentiate themselves rather than trying to do it all. That includes everything from cost to market opportunities.

LPHP: How does system power, as opposed to SoC power, affect signoff?
Yang: This was the rationale for the merger of ANSYS and Apache. We always believed we have to focus on system-level engineering and simulation-driven product development. Semiconductor ICs are the most power-hungry part of the system. So how do we bring the whole solution to the system level. One way is model exchange. We try to do this by allowing each of the design discipline to work within their environment. So the chip designer uses our tools to analyze the power behavior of the chip to create a power model. That power model can be handed off to the package, board and system guys, who can use this power model to predict the power behavior at the system level. That includes power consumption, power-induced noise and electromagnetic interference—these are all important power-related characteristics of the system. We need to connect the dots with all the visibility of the components.