What’s changing at the leading edge of Moore’s Law and why those changes are so important.
Soitec’s Steve Longoria talks with Semiconductor Manufacturing and Design about what’s changing at the leading edge of Moore’s Law and why those changes are necessary.
AMD CTO Mark Papermaster talks about why heterogeneous architectures will be needed to achieve improvements in PPA.
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New capacity planned for 2024, but production will depend on equipment availability.
Steps are being taken to minimize problems, but they will take years to implement.
Number of options is growing, but so is the list of tradeoffs.
Increased transistor density and utilization are creating memory performance issues.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
The industry reached an inflection point where analog is getting a fresh look, but digital will not cede ground readily.
100% inspection, more data, and traceability will reduce assembly defects plaguing automotive customer returns.
Engineers are finding ways to effectively thermally dissipate heat from complex modules.
Some of the less common considerations for assessing the suitability of a system for high-performance workloads.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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