Bringing Electrical Info To Design’s Forefront

Efforts are underway to improve the SoC design flow by bringing more electrical information forward.

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By Ann Steffora Mutschler
To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process.

The analysis includes parasitic extraction of interconnect and device parasitics, electromigration, IR drop, ESD (electrostatic discharge), as well as re-simulation using layout-based parasitics. It runs from the early design stages through to the board space, where parasitics from the layout are extracted and moved back to the simulation environment to optimize the design so it can be tweaked prior to finalization.

“The three big things that you worry about in semiconductor are performance (how fast is it), how much area does it take (Moore’s Law is still scaling), and then Moore’s Law as it relates to cost,” said Jim Hogan, founding partner at Vista Ventures. “The world has changed a little bit as it moves to smaller geometries. One of the big changes is that there is so much variability introduced in lithography, for example. What you want to do is manage that variability as much as you can. The problem is that the variability of the light, how we project the light and how we print the device is influenced by what’s around it. That influence changes the way it’s printed and anytime that happens, it changes electrical characteristics of the transistor and the circuit that the transistor is in.”

As such, if design teams could have knowledge of what is printed and then could describe that or model it effectively electrically, and then correspondingly simulate that, there would be a closed loop system to deal with variability immediately—and hopefully be able to correct or optimize for it, he suggested.

Looking at it from another point of view, Hogan observed that most chipmakers use a commercial foundry these days. These commercial foundries print their transistor models, in particular, and these transistor models are generally always in the spot where they can guarantee the performance of the transistor. “The problem is that if everybody used that transistor, there would be no competitive differentiation in the circuit, so everybody tries to open up that window a bit more. And that’s the electrical window. This ability to tie the physical design to electrical performance and then electrical design and optimization is increasingly the way we have to go. As a result, there’s a lot more data, and there’s a lot more time and a lot more things for the designer to do. It’s a more difficult problem.”

These issues have not gone unnoticed.

Apache Design has been asking questions related to this for some time. “How do we do early predictive simulation of the design that’s about to come,” asked Aveek Sarkar, vice president of product engineering and support at Apache. “There are various aspects of this. One angle is how to make the design more architecture-aware, let’s say in the power grid, for electromigration, for voltage drop or even the package design. How do we make it more aware of the chip architecture itself? And what will chip the do logically and functionally? A lot of these decisions are typically done once the layout has been done and it’s a little late.”

Two years ago, the company rolled out technology for profiling a design at RTL to identify the areas of peak activity, areas where the activity changes drastically, and what the power grid needs to take care of in terms of supplying current. The relevant information is captured and then fed as a data model to the power grid prototyping.

There also is another angle to the electrical problem: How to take the data from the architecture level and guide early prototyping to determine what the chip power grid needs to look like, as well as the different kinds of packages that can be considered for the chip.

“When we do RTL power analysis, everybody is beginning to appreciate the benefits of that. It runs much faster, you don’t have to wait for a gate-level synthesis to be done, you can get early visibility, and more importantly, you can understand where the power is getting wasted and you can track it through the entire RTL development cycle. You can explore different architectures … without having to go through the whole synthesis flow,” Sarkar explained.

The challenge with that, however, especially in the more advanced technology nodes, is maintaining the accuracy against the gate-level reference. Apache asserted that it pioneered the approach of looking at the layout and creating models so that the RTL power analysis is layout aware, in a sense.

“We’re looking at the kind of interconnect structures that you will be using post-routing. What are the types of cells that the synthesis flow will end up using? We profile existing designs, we create models that we then feed back to the RTL power analysis flow so that the power analysis number can be bounded and that gives the designers confidence,” he added.

Moving away from serial
In an effort to move design teams away from a serial type of design flow, Cadence also is making strides here.

“Regardless of the process node, circuit designers have always struggled that they get to a point in the design process where they must stop their work,” said John Stabenow, group director of Virtuoso product marketing at Cadence. “They have simulations running on the ideal models, maybe they’ve done some parasitic estimations, but at some point they must stop, they must hand off to the layout designer the schematic and say, ‘Please go produce a layout view so that I can do an extraction of the kinds of parasitics I’m going to actually get in the layout view.’ That process is a serial process, so the circuit designer does their work, they ‘throw it over the wall’ to the layout designer, and the layout designer then goes off and does their work. They must get to an LVS clean and presumably DRC clean place too, where the LVS is an input to then the extraction step. That extraction leads both to Rs and Cs—the parasitic resimulation—but also leads into the EmIR flow.”

That serial process inevitably buries problems within the layout that a layout designer won’t know they’re creating. Even though they work very hard to try to avoid it from their own experience, they just never know because it’s very dependent on circuit performance and simulations, he said.

Cadence said it has broken down the barrier about needing an LVS-clean layout. Stabenow explained that as the circuit designer does their work, they get to a place where they are feeling comfortable with their simulation results based on ideal models or maybe some estimated parasitics and then they say to the layout designer, ‘Begin layout.’ In older process nodes, where layout-dependent effect is not as critical, they would start doing their layout. Now, the company has added a 2.5D homegrown extraction engine into its layout tool.

“We are able to not need LVS because in our layout environment we have a notion of connectivity, anyway, so we can keep track of what devices are placed and not placed. We can keep track of what wires are drawn and what wires are not drawn. What we can do because of that is map real parasitic information back to the schematic where we map the net names and the device names, whereas if you tried to throw it over to an extraction engine, those names would be unusable on the back annotation part,” he said.

What this means is that the layout designer can now begin to build the layout incrementally and with the extraction engine running they actually are saving these extracted views and the circuit designer can choose at any point to view them. This could be especially handy for geographically dispersed design teams.

“The circuit designer can be re-simulating as they go but even more useful is that during their simulations there’s technology in the front end that allows them to understand their sensitivity to parasitics, resistance on lines, capacitances, coupling capacitances, so through the circuit design process they actually can determine design constraints like max resistance on this net 1 and they can pass that constraint forward to the layout designer. Not only do they have the extraction engine working for them to send information back, but the constraint system can tell them while they’re drawing are they or are they not meeting the design requirement. Basically it’s kind of like preventing the electrical errors before they start. We have ways to detect DRC errors as you draw now we have the way to detect electrical errors as you draw,” Stabenow said.

Other pieces of the electrically-aware design flow beyond the parasitic extraction is electromigration (EM) checking, which is a problem at any process node depending on the circuit. Even very old process nodes running high-voltage designs for automotive applications, for example, have very stringent life expectancy types of problems. At advanced process nodes, the EM problem gets even worse. ESD is also a problem that becoming more critical to address.

But with a number of vendors now working on these issues, sharing electrical information earlier in the design process will only get easier and more automated—and that will benefit designers globally.