tag: RTL power analysis

Achieving Consistent RTL Power Accuracy
By Synopsys - 23 May, 2023 - Comments: 0

Are you struggling to accurately estimate RTL power consumption early in your design process? RTL power estimation can be inaccurate due to the complexity of the designs, the various power domains, and the use of multiple tools in the design process. Designers can make effective power-performance-area tradeoffs early by using a holistic methodology that includes both architectural and micro-arc... » read more

Low-Power Design Is A Corporate Mindset At ARM
By Mentor, a Siemens Business - 07 Dec, 2016 - Comments: 0

The use of the PowerPro platform in the methodology outlined in this paper provides ARM with an RTL design flow which is power-centric. The ability to perform daily RTL power analysis at the block/unit level provides rapid turnaround on the power trend, while weekly analysis provides more complete benchmark reference metrics. To read more, click here. » read more

Doing More With RTL Power Analysis: Smart Synthesis Architecture
By Anand Iyer - 13 Aug, 2015 - Comments: 0

Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Low Power Design: RTL Power Analysis
By Anand Iyer - 11 Sep, 2014 - Comments: 0

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Wanted: ESL Power Design Flow
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor. Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by w... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy