Wanted: ESL Power Design Flow

Much still has to be done for a higher-than-RTL level of abstraction, and it can’t just come from one vendor.


In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor.

Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by working closely with the eco-system of an IP provider and a system company.

Further, Vic Kulkarni, general manager and senior VP of Apache’s RTL business unit asserts that the industry needs to work together to get the following flow working:

  1. Create TLM models that provide visibility into the internal state of large IP blocks. Just watching transactions on ports of IP will not provide the level of accuracy designers will want.
  2. Perform a SystemC simulation outputting transactions for applications you want running.
  3. Synthesize the resulting SystemC, combining it with existing RTL representing legacy blocks to create an RTL representation of the design.
  4. Have adapters that translate the transactions into RTL signal toggles.
  5. Perform an RTL power analysis.
  6. Back annotate power data back to the ESL synthesis/simulation environment.

Shabtay Matalon, Mentor’s ESL market development manager agreed there is a need to work with other vendors in this area. “We can provide specifically two elements: the education and the automation piece. Mentor looks to IP partners for collaboration and an ecosystem because at the end of the day, power has a high dependency on the process technology for the IP. And it also relies on the knowledge of the IP providers of their technology. We are collaborating with IP providers in this area.”

Many IP providers realize they need to provide TLMs that contain the functionality and that are both loosely timed and approximately timed with much better timing, and then at the same level there is a need for IP providers to also at least provide the information and then maybe even the models that can define power at the TLM, he explained. “That’s where collaboration is taking place, specifically because, for example, if you look into an SoC one of the major consumers of power can be the embedded processor. Single core, multi-core, are consumers of power and the customer is not actually designing this IP. They are going to third-party providers to ARM, PowerPC and Intel to provide them those models, so they are relying on the IP provider to provide them with models that capture power information. Here is where we, on the EDA side, see a need and opportunity to collaborate with the IP providers to model their IP, and also at the TLM and with power and timing, and so forth.”

With this in mind, look for new relationships to be announced, and hopefully some good progress soon towards the ESL power design flow.

~Ann Steffora Mutschler

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