September 2013 - Page 7 of 9 - Semiconductor Engineering

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Low-Power CPUs Hitting Their Stride In The Datacenter
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Without a doubt, the cloud has and continues to change the nature of the datacenter, particularly the requirements the infrastructure has to deliver. Diane Bryant, senior vice president and general manager of the Datacenter and Connected Systems Group at Intel, noted during a Webcast last week, “The infrastructure must change in support of cloud-based services.�... » read more

DDR White Paper
By Various Writers - 12 Sep, 2013 - Comments: 0

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Need For Unified Chip-Package Analysis
By Chris Ortiz - 12 Sep, 2013 - Comments: 0

For anyone involved in the system-on-chip (SoC) design cycle over the past few years, it is easy to see that the functionality of the chip has become more diverse with the addition of new features and duplication of main functions to drive higher throughput. This trend coupled with the need to maintain low power through various techniques such as voltage islands and power and clock gating have ... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Under One Roof
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Microsoft’s decision to buy Nokia’s phone business, Apple’s move to build its own chips to more effectively run its software, and Google’s effort to develop its own hardware for next-generation platforms such as Google Glass mark an interesting reversal in the electronics industry. Disaggregation was the answer to slow-moving giants such as big-iron companies. Startin... » read more

Equivalence Checking
By Joseph Hupcey III - 12 Sep, 2013 - Comments: 0

Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more

Blog Review: Sept. 11
By Ed Sperling - 11 Sep, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang has unearthed the weirdest USB video ever produced—a dancing USB lighter. The messaging is pretty bizarre, too. Cadence’s Brian Fuller takes a whirlwind tour of the engineering accomplishments for the week. Check out the T-shirt message. Clearly they’re not talking about semiconductor engineers. Mentor’s Colin Walls looks at the Lua scripting... » read more

Manufacturing Bits: Sept. 10
By Mark LaPedus - 10 Sep, 2013 - Comments: 0

Rock Around The Clock National Institute of Standards and Technology’s two experimental atomic clocks have set a new record for stability. Resembling a pendulum or metronome, NIST’s atomic clocks can swing back and forth with perfect timing for a period comparable to the age of the universe. The clocks are based on ytterbium atoms. The clock ticks are stable to within less than two part... » read more

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