Power Grid Analysis Heats Up At 20nm

Physics are bringing new challenges for power grid analysis at 20nm and below.


By Ann Steffora Mutschler
Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts.

Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving from planar to finFET transistors.
For the majority of the industry, 16 nm is where the transition will take place from planar to finFET transistors, although Intel already made its transition at 22nm.

“One of the biggest benefits of finFETs is the ability to compact the transistor area into a smaller portion of the die for the same amount of functionality,” explained Aveek Sarkar, vice president of product engineering and support at Apache Design. “The second benefit is that you can control the threshold voltage very, very closely. With the tight handling of the threshold voltage you can actually drop the supply voltage considerably and go below 1V into the 600mV or 700mV range.”

However, problems come in when the noise margin is considered, he said, and it just becomes worse because all of a sudden the supply voltage is lower. “Let’s say the supply voltage is 700mV and you have noise because of the package due to the switching. If that noise is 100mV it becomes almost 13% to 14% of the supply voltage. When you were at 1V supply and you had 100mV noise, you had 10%. That noise is actually worsening because the finFET device has higher drive strength—about 35% more, based on what we see from literature. You are able to push current faster into the wires, so you are pushing more current and pushing it faster because you have more transistors in the same area. You are generating a lot more transient current, or current that changes over time, so the noise is obviously much higher than what it was for planar. And then the worsening fact is that your tolerance for that noise is lowered because your supply voltage is now no longer 1V, it is 700mV. The impact on the clock tree, which is the biggest victim, and the impact on the timing becomes considerable.”

Further, Sarkar noted, the impact now includes the IO, which is becoming wider to accommodate faster data rates. “The impact of voltage drop is starting to dominate the signal integrity. So it’s not only the core power grid. The I/O power grid starts to become a big problem.”

A lack of ESD protection—reliability protection—is rearing its ugly head. “In the finFET world the snap backs are no longer available, so you have to use diodes. The diodes typically end up becoming bigger in order to provide the same amount of protection and then the current density is higher and joule heating is higher so the sensitivity from an EM event just becomes worse and worse.” This translates to new concerns about how the wiring and vias impact the power grid analysis in general, he added.

Another significant aspect to 20nm is that double patterning comes into play, which has an impact on the power grid. “Any change is so big that you have to be extremely cautious, more than before, about how you do your power grid,” said Christen Decoin, product marketing manager for new and emerging markets for Calibre Design Solutions at Mentor Graphics. “That’s going to constrain your design engineer more. The power grid analysis itself it does not change much, but for the flow of power grid and the design implementation it changes a lot of things because you cannot do late changes that easily. If you modify your power grid late it is going to impact all of your coloring, all of your double patterning for all of your placement, meaning you will be restricted on modifying your power grid topology and floor plan. Some SoC providers cut the power grid to give some area to the router, and in doing so it’s going to be that much more difficult for them because they will have to perhaps cut more to have more space to be able to take into account the double patterning issues.”

Pain points
With 28nm power analysis tools already choking on designs, the challenges are steepening.

Jerry Zhao, director of product marketing for power signoff at Cadence, said accuracy is a given for any signoff tool. “[Users] always want you to be accurate so this is the thing that is a default. They don’t even ask you in the beginning. They will say this one takes too long to signoff and the capacity is big and they can’t run it unless they go through a piecemeal type of solution, and ‘Can you do it at the full chip level?’ So capacity and performance is always number one for top-notch [users]. Some companies design very large chips and want to know how they are going to signoff. That’s the first one they want. The other one is, ‘How am I going to fix it if I have a power grid problem?’ That’s to the implementation tool as well as the downstream system tool.”

Packaging adds another challenge because the package also has a load. “That’s going to play a role on your die and vice versa—your die is going to have impact on your package design,” Zhao said. “Basically this power grid goes up to the implementation and goes down to the system tool but in the middle, the power signoff is also related to the timing signoff, those are electrical signoff and when you have a voltage drop, your critical path may change, the timing may not be met, so how are you going to tie together over there?”

In addition, Decoin reiterated that 20, 16 and 14nm are going to be very different in terms of capacity and size. Existing solutions already have a hard time at 28nm and already are exhibiting capacity and performance issues. “At 20nm, the [die] size is going to roughly double, and 16nm and 14nm is going to increase by 20% to 35%. This means that already on the capacity and turnaround time the tools are going to be really, really choking. On the flow you’re going to have to stop the idea that you going to know what’s going to happen. If you take the flow at 28nm and above, people could say, ‘OK, I roughly know what kind of power grid I have to generate to be sure that when I’m going to do my analysis at the signoff I’m not going to have a big roadblock. Perhaps I will have minor issues to solve.’”

At 20nm and below, however, it seems likely that early stage power analysis is going to be required with more constraints and perhaps more rigid power budgets, he said. “Let’s say if you have blocks and you do your power grid analysis at the floorplan level right now, you have a rough estimate of your block, and what they are going to consume. When you move from planar to finFET you will need to take into account much more current consumption—this is what we think. And if you don’t do that early enough then at the end, you will do your signoff and you’re going to have voltage drops you weren’t expecting because it’s the first time you are doing finFET. And the experience of people is not going to help because nobody has really experienced finFET yet.”

Also, Decoin believes the biggest issue at 16nm and below for power analysis tools is going to be that they do not have an upstream flow. “This is at the beginning of the implementation of your place and route blocks, because after that you will not be able to touch your power grid due to the double patterning issues. The issue you will get at 16nm and 14nm with the capacitance of the transistor is going to be much bigger and you have to take that into account early or the timing margin is going to disappear and you will not be able to resolve voltage drop errors.”

In Zhao’s mind, the best way to handle this is to have a single platform wherein timing is run first, then power. After that, power information should be back annotated to the timer and the design is timed at the new voltage.

“The direction for the industry to solve this very complex problem is that you need to have an ecosystem for it, not only in the timing but also the extraction,” Zhao said. “The power grid, after all, is the extracted power grid—the metals, the vias, the Rs and the Cs. So the extraction tool should also have signoff quality. It should be certified by the foundry.”

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