February 2015 - Page 4 of 10 - Semiconductor Engineering


How To Extend Litho Scaling


IC mask [getkc id="80" comment="lithography"] today is sophisticated and complex. It's also a work in progress with a lot of unknowns as the industry struggles to increase productivity while reducing risk. The bulk of the work currently is focused on trying to figure out what would be a practical scheme for patterning lithography that could be used at 10nm and 7nm, said Gandharv Bhatara, Ca... » read more

3D NAND Market Heats Up


After some delays and uncertainty in past years, the 3D NAND market is finally heating up. In 2013 and 2014, Samsung was the only vendor participating in the 3D NAND market. Most other suppliers were supposed to ship 3D NAND devices in volumes last year, but vendors pushed out their production dates for various business and technical reasons. Going into 2015, [getentity id="22865" e_nam... » read more

Demonstrating The Benefits Of Source-Mask Optimization And Enabling Technologies Through Experiment And Simulations


In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithograp... » read more

Will 10nm Be The Last Big Node?


There is a great deal of attention being paid to established nodes these days and everything up to and including 10nm. What comes after that remains a mystery. Intel and a handful of others will keep pushing to the next nodes, of course. Still, where the commercial foundries—including Intel—place their next big bets is a matter of ongoing debate. There is no doubt that 7nm and 5nm will b... » read more

The Power Of Collaboration: Solutions For Improving Manufacturing


The Fab Owners Association (FOA) held its third annual Collaborative Forum in Santa Clara, Calif., earlier this month. The focus of this event was to discuss how companies are able to work together to improve manufacturing efficiencies in wafer fabs. The forum is by invite only to FOA members, and I was invited to make a presentation on the market trends due to the impact of MEMS and Sensors. ... » read more

One-On-One: Dave Hemker


Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

Talking About Dark Silicon


Back in January, my article on dark silicon referenced work done by Michael Taylor and his research group at UC San Diego. I wasn’t able to arrange an interview with Dr. Taylor in time for that article, but we did have an extended conversation earlier this week. He pointed out that, while further decreases in threshold voltage are constrained by device leakage, the energy consumed by a circui... » read more

Searching For Rare Earths Again


Rare earths are back in the spotlight again. Rare earths are chemical elements found in the Earth’s crust. They are used in cars, consumer electronics, computers, communications, clean energy and defense systems. The big market for rare earths is magnets. In semiconductor production, rare earths are used in high-k dielectrics, CMP slurries and other applications. Last year, the World Tr... » read more

Still Waiting For III-V Chips


For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

Balancing On The Color Density Tightrope


Balancing on wobbly tightropes is something that chip designers get pretty good at. For instance, there is a fine balance between optimizing performance and minimizing leakage in a design layout. Dealing with the new requirements that multi-patterning (MP) introduces into a design flow creates many new tightropes to walk. I tiptoed out on one of the rarely talked about ones in my last article�... » read more

← Older posts Newer posts →