August 2016 - Page 3 of 11 - Semiconductor Engineering

Got System Cache?
By Rajesh Ramanujam - 25 Aug, 2016 - Comments: 0

Similar to the world we live in, a coherent SoC system has truly become a hodgepodge of often conflicting desires, wants, and needs. While some traffic flows are highly sensitive to CAS latency, others have rigid coherent bandwidth requirements, and others are more concerned with “must have” real-time needs to fulfill their tasks. Varying vastly from "must haves" to "best-effort," finding t... » read more

The Forest And The Trees
By Malte Doerper - 25 Aug, 2016 - Comments: 0

If you’re deep into the details, it can be hard to see the bigger picture of what lies ahead. There is a saying for this, of course, which everyone knows: “He can’t see the forest for the trees.” So the solution is to rise above the trees to gain a better view. Interestingly, many benefits for using virtual prototypes for early software development result from the high level of a... » read more

Putting Design Back Into DFT
By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

Automation: When Should We Stop?
By Mike Gianfagna - 25 Aug, 2016 - Comments: 0

Automating tasks has become quite popular. Driver assist is a good example. So is any machine learning application. You may have noticed that you can now get deliveries in less than 24 hours on Amazon. There is huge automation behind that service. So the question becomes, when is enough, enough? When does automation hit the law of diminishing return? When does this all become “creeping featur... » read more

The Rise Of Complex Debug On Heterogeneous Multicore SoCs
By Kathy Tufto - 25 Aug, 2016 - Comments: 0

When projects move away from discrete development of loosely coupled systems to an integrated heterogeneous environment, elephantine debugging challenges are created. These challenges do not exist during discrete development because developers are able to design, develop, test, and optimize within the confines of their own device. But when consolidating heterogeneous systems, developers and ... » read more

It’s Time To Get Your University In Sync With Zynq
By Aldec - 25 Aug, 2016 - Comments: 0

By Zach Nelson It’s time for universities to say goodbye to their outdated FPGA boards and introduce the Xilinx Zynq chip. The chip is a device which combines an FPGA fabric with a processing unit. The chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities. What can Zynq do? The Zynq ... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

UI Development And Graphics Strategies For Today’s Embedded Devices: Performance Matters!
By Mentor, a Siemens Business - 24 Aug, 2016 - Comments: 0

The importance of getting your interactive graphical user interface (UI) right for the end user is absolutely critical to the success of any project. By understanding the most common occurring issues, or issues cited as the most frustrating/degrading experiences in the UI experience, and by taking a holistic view of the system across layers (OS, middleware, application) with these specific UI a... » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP
By Arteris - 24 Aug, 2016 - Comments: 0

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more

Stepping Back From Scaling
By Ed Sperling - 24 Aug, 2016 - Comments: 0

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

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