January 2018 - Page 3 of 13 - Semiconductor Engineering

3D Extraction Necessities For 5nm And Below
By Ruben Molina - 25 Jan, 2018 - Comments: 0

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more impo... » read more

It Takes A Village… To Develop And Verify SoCs
By Frank Schirrmeister - 25 Jan, 2018 - Comments: 0

In my last blog post from 2017, “Design Chains Will Drive The Top 5 EDA Trends In 2018,” I had pointed to the importance of ecosystems for electronics development in general. From an EDA perspective, it also takes a village to shepherd the actual chip development with its complex verification and software development tasks. And the types of partnerships often depend on the application domai... » read more

Analyzing Data Differently
By Sunil Sahoo - 25 Jan, 2018 - Comments: 0

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

7/5nm Timing Closure Intensifies
By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

In Case You Missed It
By Mike Gianfagna - 25 Jan, 2018 - Comments: 0

We recently held two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic p... » read more

Predictions: Methodologies And Tools
By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer
By Technical Paper Link - 24 Jan, 2018 - Comments: 1

Source: UNSW Sydney Authors: M. Veldhorst (1,2),  H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Achieving ISO 26262 Software Tool Confidence For Improved Automotive Functional Safety
By Synopsys - 24 Jan, 2018 - Comments: 0

Achieving ISO 26262 Software Tool Confidence for Improved Automotive Functional Safety The rapid adoption of advanced electronic systems in automobiles has prompted the automotive industry to develop the ISO 26262 functional safety standard to address the potential risks associated with failures in these systems. ISO 26262 is derived from the more general IEC 61508 standard and defines requirem... » read more

Heatsinks Here, There, Everywhere!
By Mentor, a Siemens Business - 24 Jan, 2018 - Comments: 0

Heatsinks are often perceived to be the magic answer to all electronics cooling challenges. A heatsink makes heat spread out, so that it passes to the air over a much larger surface area than it would otherwise. Air then carries the heat away, cooling the electronics that generated it. So, why not place a heatsink on top of any thermally critical component? To read more, click here. » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm
By Cadence - 24 Jan, 2018 - Comments: 0

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy