28nm Chip-Package Interactions In Large eWLB FO-WLP

To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO’s, multi-chips, heterogeneous integration and 3D SiP. In particular, Embedded Wafer Level BGA (eWLB) is a fan- out WLP solution which can enable applications that require higher input/output (I/O) density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also provides integration of multiple dies vertically and horizontally in a single package without substrates.

For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in 10×10~15x15mm 28nm eWLB fan-out WLP with multiple redistribution layers (RDLs). Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Electrical characterization was also studied for both simulation and experimental works. The influence of structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

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