3D Stacked Die Create Unique Test Issues

Normal testing procedures of pins needs to be changed with TSVs; temperature fluctuations and silicon defects create new challenges.


By Ann Steffora Mutschler
While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple.

There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And at each level, there are phenomena that impact quality and that lead to potential defects, said Ed Malloy, product manager for Encounter Test at Cadence Design Systems.

At the wafer level are all of the challenges normally seen in a non-3D scenario, including design and process related defects—traditionally called “stuck at” and delay-based defects, which are timing or process-related defects. With the “stuck at” or static types of defects at the wafer level, the dynamic defects are typically process-related, where a higher resistance might occur on a trace on the die that slows the signal down.

Both of these challenges become even more complicated by the stacking process. “As you stack these devices, there are thermal impacts that need to be modeled and understood,” Malloy said. “So as we go down the process curve the cell behavior becomes more widely varying depending on your process and your temperature. The temperature fluctuations have a significant impact on the quality of your signal integrity. So if you’re not understanding the thermal characteristics or dynamics that exist between the stacked devices, then this can lead to failure.”

Effective testing of 3D integrated devices starts with having a high-quality ‘known good die’ (KGD) test, explained Greg Aldrich, director of marketing for the Silicon Test Systems group at Mentor Graphics.

“The first step in testing for a 3D package is to be able to test the wafers or the standalone die before any packaging gets started. Typically that will get done at wafer test, so you’re testing multiple wafers that will eventually get packaged together. You have to have a test that does a very high quality and tries to detect everything you can possibly detect before you start packaging the individual die.”

One of the biggest challenges with 3D stacking has to do with the number of pins because there may not be access to all of the pins during wafer probe. Many more pins are used in 3D stacking, but a large number will not get packaged. Instead, they will be attached with a through-silicon via (TSV) or in another way, and there may not be big enough probe pads to probe them during wafer test.

“Today’s probe technology is unable to handle the finer pitch and dimensions of TSV tips. The wafer has to be thinned by about 75% for them to be stacked, but what happens is that the tips of the TSVs can be exposed. So as the thinned wafer is contacted by the wafer probe there is a danger of damaging the wafer,” explained Samta Bansal, product marketing for Encounter digital implementation system, and 3D IC guru, at Cadence Design Systems.

“You may have thousands and thousands of internal pins and you are only bonding out a very small subset. So especially after you get the package together, how do you get access to everything and fully test everything from a very small number of pins?” said Mentor’s Aldrich.

Mentor does all testing through a TAP (test access port) interface, under the IEEE boundary scan specification 1149.1 that has a 5-pin interface for test access. For example, all of its BIST is initiated and results gathered through the TAP interface.

A second piece of the 3D testing involves the interconnect between the package to verify everything that goes through the TSVs, as well as things that can be bonded out and packaged separately, he said. In testing the interconnect there could be two SoCs stacked on the package, for example, and there may be a lot of different types of interfaces between those SoCs. Some may be standard digital, some may be analog signals, and some may be high-speed serial-bus interfaces. Another scenario could be a memory chip, like a DRAM, stacked on top of an SoC. In both cases, the SoCs or the memory must be fully tested once it is sitting in the package.

Aldrich noted that Mentor is leveraging all of its technology in a different methodology. “For example, for testing a memory chip that’s sitting on top of an SoC, we can take our memory BIST and instead of putting it on the same die that the memory exists—which is what we would typically do for embedded memory—we can put it on the SoC and then interface the BIST for that memory through the normal bus interface between the memory and the DRAM. So with the memory BIST logic sitting on the SoC we can then test the DRAM chip itself. It’s a different methodology of using some of the BIST logic that we have.”

For testing the die-to-die interconnect, IEEE 1149.1, the boundary scan standard for single-ended digital signals can be used to test all the signals in between SoCs in a stack, and IEEE 1149.6 that is for AC coupled differential signals.

Managing power during test
As the industry moves down the process nodes, the consumption of power during test mode is impacting signal integrity of the chips, therefore power must be managed during test mode. “Traditionally test mode consumes anywhere between 2X and 5X the power of a normal functional mode. Because of the variations in the lower processes, you can’t afford to have these wider swings of power – they impact not only the signal integrity but the reliability. You can have early defects if you’re not managing power, so they can pass on a tester but fail in the field. By managing power at the wafer level, it mirrors the power consumption during functional mode – that’s an essential part of ensuring that ‘known good die’ are going into the 3D assembly process,” Cadence’s Malloy explained.

Within the 3D package device itself, power consumption must also be managed including memories, which can consume a lot of power, he said. “When they do, it affects temperature, which affects performance, and signal integrity – it’s a spiraling effect. So you have to have the capability to manage your memory tests, your logic tests and all the power. At the same time, you need to be testing areas that would potentially be susceptible to thermal effects: there may be some high risk areas that you would want to test after assembly. An easy one would be to model and test the through silicon vias and interface as well as the communication across chips. Of course you want to check the connectivity but still need to be checking some of the core logic and how it’s behaving once these devices are packaged.”

As part of a 3D stacked die methodology a test sign-off or test vector sign-off should be included in order to know where potential hot spots may be, which power analysis tools can do.

Other companies doing work with 3D ICs include Apache Design Solutions, which in last several years, has been working with a number of leading semiconductor companies including TSMC on 3D ICs. In fact, in June, TSMC included Apache’s 3D IC power and noise tools in its Reference Flow 11.0 and Analog/Mixed-Signal (AMS) Reference Flow 1.0.

The drive to reduce power and increase performance demands advanced packaging technologies such as SiP and 3D-IC/TSV. Apache recognized that these technologies pose major power, thermal, and stress challenges due to the coupling of power delivery network between digital and analog dies and their heat transfer properties. As such, Apache’s tools generate CPM and CTM as hand-off compact models representing the die power and thermal behaviors, and are extended to utilize CPM and CTM for multi-die chip-package analysis.

For additional information on this subject there are two blogs of note:

–Samta Bansal’s blog.
–Ed Malloy’s blog.

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