3D Stacking: A Reality Check

Best guesses on rollout schedules, where the trouble spots will be, and what kinds of benefits to expect.


By Ed Sperling
The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013.

While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law.

But unlike the progression of Moore’s Law so far, stacking of die will have ramifications for every part of the IC ecosystem. From a business standpoint, it holds the potential to revolutionize the speed with which chips are built for generalized as well as customized markets. From the technology side, it can radically boost performance by moving memory closer to processor cores and reducing bandwidth constraints. It also provides some of the benefits of classical scaling because it requires less power to drive signals over a shorter distance.

What is less clear is the number of obstacles that will be encountered along the way and what exactly those obstacles will be. In some cases, those obstacles are economic. How much will it cost to add an interposer layer, for example, versus a standard 2D package? In others, there are physical effects that have to be considered, such as the stress of drilling TSVs into die, thinning and handling of ultra-thin wafers and how to get heat out of a true 3D stack. And there are still questions about how all of this technology is going to be tested and verified.

Economic considerations and timing
“Initially, this is all about cost,” said Prasad Subramaniam, vice president of design technology at eSilicon. “Power may be an overarching benefit and people may pay more for that advantage initially. But first it is about cost. We believe the cost will come down over time as volume increases.”

The general consensus among companies across the supply chain is that the first stacked dies will begin to appear in volume over the next 12 months. Mainstream adoption is expected to ramp up over the next two years. That will include some true TSV-based 3D designs, which can leverage smaller form factors, as well as 2.5D, which is where the mainstream market adoption will occur.

“If you can do the chip on an MCM (multichip module) or SiP (system in package) then there’s probably no need for 2.5D,” said Subramaniam. “The real benefit is power, and if you enable more pins on a die you get more communication between multiple die. You can’t implement Wide I/O on an MCM. You can’t get the pitch to accommodate multiple signals.”

Xilinx has taken a first stab at using an interposer to link four different die. Ivo Bolsens, CTO at Xilinx, said the driving force for his company’s decision to use an interposer was yield. The success rate in producing four smaller chips is significantly higher than one large chip, even with an interposer in the middle.

Xilinx isn’t alone in trying to solve this problem. Samsung, Elpida and Micron all are sampling 3D memory chips using through-silicon vias, and STMicroelectronics and Infineon have introduced MEMS chips and sensors based upon stacked-die approaches.

“This has been a fairly rapid shift toward 3D,” said Steve Smith, senior director of platform marketing at Synopsys. “It all changed about the time Xilinx announced its prototype FPGA in October. After that, TSMC and GlobalFoundries began making noise about stacked die. The biggest benefit is that some of these chips can be designed the same way, which will increase their adoption. The only real worry is the alignment of bumps on the ‘Moore’s Law’ chips to connect to the interposer. You can do that with a spreadsheet analysis, though. There are no fancy tools required.”

Evolutionary development
As significant as stacked die are on the design and business of ICs, what is likely to unfold over the next few years is more evolutionary than revolutionary. While the memory makers develop complex architectures to improve throughput, they will mostly be packaged with existing technology that is part of an existing design methodology. In fact, some parts of design may actually get simpler.

“You can either put more logic on the chip or shrink the die,” said Smith. “But when you look at traditional place and route, that’s a bunch of black boxes. There are a lot of big macro blocks around the periphery. That’s where you put analog interfaces, and you can attach to memory in the middle.”

Even testing in 2.5D is not that difficult. Some will have to include built-in self-test (BiST) for embedded technology that cannot be easily tested, but for the most part there are no surprises in 2.5D configurations. Things get dramatically more difficult in true 3D packages, however.

“The question is how you bring all of these elements together to come up with a fully functional 3D device,” said Steve Pateras, product marketing director for silicon test at Mentor Graphics. “What’s happened in the industry is we’ve become very fragmented over the past 10 to 20 years. This is going to drive a blending of the IC fab with the packaging house to provide this kind of solution. Once this happens, there will be a lot of people out there who say they need this.”

What’s missing
There will also need to be new EDA tools developed—or at least significant extensions to existing tools—to make all of this work.

“With TSVs it all depends on what’s the pitch,” said Mike Gianfagna, vice president of marketing at Atrenta. “The denser the pitch the more packaging, and the cost in yield loss goes up exponentially. There also need to be thermal and stress models and a better way of calibrating these models, which right now is weak, at best. And with EDA tools, you need good thermal and mechanical stress models.”

All of this will take time to develop, of course. So will the tools to actually handle extremely thin die. Interposers are regular thickness, but in a true 3D stack the layers are much thinner and can easily break using current technology.
Beyond that, there also will have to be a business case for more companies to move to true 3D before that becomes a mainstream technology.

“Designs drive the process,” said Gianfagna. “EDA tools can work but without good data that doesn’t really matter.”

The future
Still, the number of choices that will become available once the semiconductor ecosystem adjusts and the processes are developed are enormous. Just as process technology has become refined to the atomic level, stacking of die adds a level of granularity for specific markets that addresses what can be put together quickly and for whom. A 3D stack may include a MEMS chip or an analog sensor built on the same base platform, for example, with minimal additional development time or cost.

And with foundry equipment expected to cost tens of billions of dollars at 14nm, there may be little choice but to pursue this path. The progression of Moore’s Law may continue intact—the number of transistors in a chip, rather than on a die will continue to grow—but not necessarily in the same plane or even from the same company.