3D Standards For The Real World

By Pallab Chatterjee
Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain.

This was quite evident at a recent DesignCon panel dicussion on 3D die and assembly standards. The panelists—Riko Radojcic of Qualcomm, Sumit DasGupta of Si2, Liam Madden of Xilinx, Raj Jammy of SEMATECH and Jim Hogan of Vista Ventures—had widely different views about what needs to be done.

Both Qualcomm and Xilinx are in production with products that use TSVs and other stacked die technologies. Sematech and Si2 are focused on future directions for being able to implement what these companies have accomplished, seeking commonality in process and design across dissimilar businesses and markets.

Hogan zeroed in on the realities of production and getting parts into the marketplace, downplaying standards that result in everyone working together happily. The challenge, he said, is the rules for these stacked die are based on what you do with them.

The Xilinx product has a fixed pattern logic array (FPGA core) and fixed memory blocks connected together in a pattern that conforms to both its design architecture as well as its design software base. These pin placements, pad locations on the die, and stacking methodology are not necessarily applicable to other vendors or custom designers that could benefit from standardization of Xilinx’s tooling. As a result, moving forward without a standard is not a big deal for this application.

Qualcomm has a similar situation for its stacked die, which is targeted at cell phones. The company’s RF and logic cores and second chip memories, which are driving the use of stacked die, have different I/O issues. Compared with Xilinx’s application, Qualcomm’s has different pin counts, different performance for these connections and a much different reach. This is a custom processor that can be laid out over the local RAM, creating a clock-optimized design that minimizes the delay path for the system design.

Based on the unit being created—whether it’s a smart phone, feature phone, tablet, TV or set-top box—there are different assembly guidelines and goals for the 3D stacking. These designs heavily utilize traditional edge-based pin connections. Qualcomm already has a history of stacked die production. It has used this knowledge base to make more aggressive chipsets and product solutions, so at this time sharing that marketplace information has a limited value.

Hogan noted there is a need for commonality in processes, so every like microprocessor can contact a standard product memory, but custom processors and custom memories need not conform. It’s the same with standard logic functions being available as both MPW samples and DFW that are implemented as a high-level standard function IP. The challenge becomes when is it IP and when is it package assembly? While the technical model may want to have standards in the loop to address a TTM reduction, the business model for incorporating those standards is behind the pace of implementation that is dictated by the product rollout schedules. The market cannot wait, and products have to be shipped.

Hogan also brought up the concept of IP for the 3D interconnect and its encompassing system. If there are standard locations (similar to the JEDEC ones that are already in progress), will these include electrical specs, thermal and materials models, abstracted simulation models, reliability information, and test for both sides of the interconnect point as well as the interconnect point itself? Creating a specification of location and order without these aspects does not help the time-to-market challenge facing the semiconductor industry.

Unlike the power supply debates, which were fostered as two standards from competing EDA companies with differing politics of design—the 3D market is not a single problem with different approaches. It includes different design applications in different manufacturing chains that require some pin commonality.