7nm Design Success Necessitates A Multi-Physics Approach

Whether you are designing an energy efficient mobile device, or an ADAS platform with stringent reliability requirements, or a high performance enterprise networking system, chips fabricated on advanced technologies such as 7-nanometer (nm) process and 2.5/3D or wafer level packaging can provide several advantages. Designs using these technologies consume less power while delivering higher throughput and performance gains. They enable you to design chips with smaller form factor with higher levels of integration.

However, these benefits come with challenges that cannot be sufficiently addressed by traditional design and analysis methodologies. Following a traditional silo based design approach, chip, package, board and system designers use pre-determined margins to design their specific component. These designs are done by separate teams or even separate companies with very little communication. In addition, existing tools limit each design team to analyze and resolve single physics (timing, power, temperature, etc.) at a time without any visibility into interactions between multiple physics.

Need for multi-domain/multi-physics co-analysis
With tighter noise margins, higher junction temperatures and greater risk from reliability failures, it is no longer sufficient to design and analyze each component separately, nor is it acceptable to consider only single physics at a time. Package or board parasitics can have significant impact on chips’ performance. Likewise, chips’ current distribution can affect the systems’ power integrity (PI), signal integrity (SI) temperature and reliability.

Understanding and mitigating power and signal noise impact ensures safe and reliable operation of these advanced N7 devices, which in turn is critical to the success of your product. To achieve this, you need to adopt a holistic approach with coupled analysis between all the components of the product – from the chip(s) to package(s) to board(s) to the system. You have to be able to optimize your design for power integrity, signal integrity and thermal management, as well as ensure that it meets electro-migration (EM), electro-static discharge (ESD), electro-magnetic interference (EMI), and stress requirements.

Consider the fact that power delivery network (PDN) spans across a broad frequency spectrum – from MHz at the board level to multi-GHz at the chip level. In order to optimize PDN for power integrity, you need to analyze across chip, package and system. Each level (chip, package, PCB) has widely differing impedances, which results in dramatically different response time. In addition, the current signature of PDN is a function of slew rate and is closely related to frequency response. As these factors are coupled across frequency domains, analysis that decouples each domain will be inevitably inaccurate and severely limits your ability to make informed design trade-off decisions.

As shown in example below, to meet the target impedance of 400 mΩ across the entire frequency spectrum, decoupled analyses will direct you to add a large amount of decaps on the board, adversely impacting the cost of the product. However, analyzing the entire PDN that couples die level impedance demonstrates that you can meet your target with more modest improvements to the board and package. Chip-package-system (CPS) co-design and co-optimization helps you understand the impact each domain has on each other and enables you to produce more cost-effective and reliable designs.

Requirements for chip-package-system co-design/co-analysis
A true co-design and co-analysis methodology requires accurate modeling of various physics such as power, SI and thermal for chip, package and the board. The modeling approaches need to provide sufficient details, yet optimized for efficient simulation. The environment needs to support seamless integration with visibility for productive debug and analysis across multiple domains. It needs to be reasonably fast so design teams can perform several iterations of “what-if” analysis to ensure optimal design.

System-aware chip-level power analysis
Today, the inclusion of package parasitics into chip level analysis has become a standard practice. However, many system functions, especially those used in mobile and ADAS applications operate in a low to mid frequency range which can closely couple to package and board PDN. This requires the chip/package analysis to include the PDN model of the board for more accurate results.

Considering the impact of package and board parasitics on your chip’s performance, requires high capacity, high performance solution that can analyze full package and board, along with die level model, as well as the ability to quickly extract these large structures. The environment also needs to provide seamless integration of varying models with the ability to view, debug and optimize the coupled effects on chip’s hotspots, temperature profile and reliability such as EM and ESD.

Chip-aware system-level PI/SI/thermal and EMI analysis
Traditional system-level power analysis relies on AC analysis of package and board for self-impedance alone. However, fixing the design for a specific resonance with higher than target impedance can lead to erroneous results unless you consider the entire PDN from die, package and board. Not only can this decision based on a silo-based approach produce a sub-optimal design, it can create unexpected harmonics with chip’s dominant frequency and adversely increase its dynamic voltage drop. This can impact the products’ performance and eventually its’ market acceptance and success. Chip-aware system-level power analysis requires an accurate model of the chip that reflects current flow and parasitics at each bump, as well as its coupling with every other port providing both temporal and spatial visibility into the chip’s electrical behavior. If you are a package or board engineer or if you work closely with package/board engineers, you or your colleagues can use this model to perform DC and AC analyses of entire PDN and optimize system power delivery. DC analysis can help you detect package and board level PDN issues such as missing vias or broken network. AC analysis can help predict performance degradation caused by insufficient reactive response in passive components in the package and board PDN.

Traditionally, signal integrity analyses either looks at impedance matching and considers only the SI portion of the design, or uses IBIS or transistor level models for SI and PI effects. However, simultaneous switching output (SSO) noise can have significant impact on system performance and functionality, which cannot be captured properly with an SI only approach. In order to detect and resolve SSO noise, you need to consider the effects of crosstalk between package and PCB signal nets, as well as power-ground noise caused by IO’s switching current and package/PCB inductance.  While an IBIS model is simpler and faster to use, it does not include intrinsic parasitics or the complete switching activity and resulting power-ground noise. A transistor model may be more accurate, but the Spice capacity limitations affect the ability to simulate an entire bank. For a most accurate and comprehensive SSO analysis, the simulation needs to include full IO bank so that you can understand the complete switching activity, the resulting power-ground noise, and how it impacts IO timing.

Thermal integrity plays a critical role in overall system reliability and robustness. There is a close interaction between the switching activity of a chip and the resulting chip-package power profile, chip-package metallization, system boundary conditions, and cooling system design. The temperature profile of the chip on the other hand affects the systems’ long-term reliability. For certain mission-critical applications such as air-bag deployment devices, it can also affect the transient behavior. Therefore, it is important to perform chip-aware system-level thermal analysis to achieve CPS thermal integrity and power-thermal convergence. To gain realistic view of the system-level thermal performance, a detailed chip-level thermal model used in CPS thermal analysis need to include temperature-dependent tile-based power density and per layer metal density maps, as well as wire temperature with device self-heating and Joule heating effects which are becoming increasingly important for 7nm devices.

Traditional system-level emission models are based on a simplified layout of a chip that can only be used to perform relative comparison between different layouts. This approach is insufficient for systems using chips designed at 7nm with higher current density, faster switching and smaller footprint. In order to accurately predict system-level EMI, you need to include real noise source from chip activities into the analysis. Such information encapsulated in chip-level EMI model considers noise generated by multiple simultaneously switching of logic transistors and pad drivers, as well as various noise source coupling such as core switching noise to pad supply pins and pad switching noise to other pad signal pins.

Packaging choices can have considerable impact on system-level reliability such as EM, ESD, and EMI. 2.5/3D or wafer-level packaging result in close proximity between the die and wafer or interposer interconnects. This increases thermal hotspots, which in turn can effect EM and ESD at both chip and system level. In addition, it can increase the chance for thermal-induced stress, which can lead to warping and contact separation.

Multi-domain/multi-physics simulation increases coverage and mitigates risks
By adopting a CPS co-design and co-optimization methodology where multiple domains and multiple physics are simultaneously analyzed, you can make better design decisions for your chip, package and the system. By understanding how chip-level power noise impact package and PCB designs, you can improve your design cost and performance by optimizing decap sizing and placement. Considering the impact of power noise on timing allows you to gain more accurate view of jitter. Its impact on temperature helps you identify thermal hotspots that can increase EM failure risks.

At 7nm processes, each component cannot be designed in isolation. The interdependencies between multiple domains (chip, package, board, etc.) as well multiple physics (power, timing, thermal, stress, reliability) need to be considered to increase confidence in design verification coverage. The success of your end product will require a holistic approach to design and verification. For more information, check out this white paper.