A technical paper titled “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures” was published by researchers at ETH Zurich and University of Bologna.
“Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet architectures is huge as there are many degrees of freedom such as the number, size and placement of chiplets, the topology of the inter-chiplet interconnect and many more. Existing tools for cost and performance prediction are often too slow to explore this design space. We present RapidChiplet, a fast, open-source toolchain to predict latency and throughput of the inter-chiplet interconnect, as well as a chip’s manufacturing cost and thermal stability.”
Find the technical paper here. Published November 2023 (preprint).
Iff, Patrick, Benigna Bruggmann, Maciej Besta, Luca Benini, and Torsten Hoefler. “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures.” arXiv preprint arXiv:2311.06081 (2023).
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